@@ -161,6 +161,9 @@ struct davinci_mcbsp_dev {
int tdm_slots;
int slot_width;
+
+ bool tx_framing_bit;
+ bool rx_framing_bit;
};
static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
@@ -580,6 +583,15 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
}
+ if (dev->tx_framing_bit) {
+ xcr &= ~DAVINCI_MCBSP_XCR_XDATDLY(1);
+ xcr |= DAVINCI_MCBSP_XCR_XDATDLY(2);
+ }
+ if (dev->rx_framing_bit) {
+ rcr &= ~DAVINCI_MCBSP_RCR_RDATDLY(1);
+ rcr |= DAVINCI_MCBSP_RCR_RDATDLY(2);
+ }
+
if (params_channels(params) == 2) {
element_cnt = 2;
if (double_fmt[fmt] && dev->enable_channel_combine) {
@@ -796,6 +808,9 @@ static int davinci_i2s_probe(struct platform_device *pdev)
dev->base = io_base;
+ dev->tx_framing_bit = of_property_read_bool(pdev->dev.of_node, "ti,T1-framing-tx");
+ dev->rx_framing_bit = of_property_read_bool(pdev->dev.of_node, "ti,T1-framing-rx");
+
/* setup DMA, first TX, then RX */
dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
dma_data->addr = (dma_addr_t)(mem->start + DAVINCI_MCBSP_DXR_REG);
McBSP's data delay can be configured from 0 to 2 bit clock periods. 0 is used for DSP_B format, 1 is used for DSP_A format, 2 is unused. A data delay of 2 bit clock periods can be used to interface to 'T1 framing' devices where data stream is preceded by a 'framing bit'. On transmission, McBSP inserts a blank period (high-impedance period) before the first data bit to leave an opportunity for other devices to set this 'framing bit'. On reception, McBSP discards the 'framing bit' that precedes the data stream. Add support for the 'framing bit' according to the 'ti,T1-framing-[tx/rx]' device-tree properties. If a flag is present, the data delay is set to 2 bit clock periods regardless of the selected DAI format. Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com> --- sound/soc/ti/davinci-i2s.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)