From patchwork Wed Apr 3 10:52:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 13615865 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B77951350EC for ; Wed, 3 Apr 2024 10:52:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712141532; cv=none; b=hS1DzJizTIWPjfM8ddgJxCP7QxeY/s70izuM08DBY8DicFNwsq/7R20CFvzTMWLQbhJDReTU1sNo3CVrL5YzNJGYAe4MZBxnENSD9xiBReHhnq+q7sRz/KwwbHdgkKOhADguwV5+aUesFvzJfLsINnP4u7XTElEO2BOBhccgtqw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712141532; c=relaxed/simple; bh=DJ552hKp//faI39FzLlhodMDp3c3XA0A0iEnFsDwwQo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YprYMSMgXEO0/XgB8NE2U7ug6GgWt/kGLz9AIO5U5GkvhOy0/dJDrHzV4TOL801u/m3KOxFPwa6Rl0uS/beHSq1hrLq2idAUTrySkOZ9SDfl9YCM+fEUwvPOhIZKzu3TfEjCJLhXugpYXqLaiO578CyUrrJuLk0cT5Ciqe1Mtpo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EnLdOlqF; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EnLdOlqF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712141531; x=1743677531; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DJ552hKp//faI39FzLlhodMDp3c3XA0A0iEnFsDwwQo=; b=EnLdOlqFK5nv//p0WSHbVGSjoACUwzJgmmkEv/mJWZkQ/1eT0nggFtp0 Zd++ze02NF717qjrDhcMn72BqfZntKOtt0cWVVYfQ1pO/XfwJx56D+jsO F2GeydMmUPfY35Z2L4O5W4BA/CpGgs6E9jClDszLm+6Yv1WoMcqtx6hDi i0Z9+6H0l6k7UCvzQnDGT2AzO0WMp9iU+zOZ8qOJ9N8dt6+G7Zw5lAOn3 cbWm0CQZsHJ8AOpyyDski5ltXUZhrUg0lyqRXe+hW2wFrqpyAGZVzL3ww DFTPtD4UZ9eGe0XANG8fKBeeLul4zAmac6Xpw81kM7Ubz9g4WP3DagJXx Q==; X-CSE-ConnectionGUID: hjaNky1rRV6MFwOprp6qdQ== X-CSE-MsgGUID: +UIR84woS5OxnTep7+lulQ== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="7212197" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="7212197" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 03:51:47 -0700 X-CSE-ConnectionGUID: 5i/9BCFsRMy0HGEkA1noog== X-CSE-MsgGUID: hH2RHnU4Qeey6kXv55sgbQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="49374785" Received: from aelgham-mobl2.ger.corp.intel.com (HELO pujfalus-desk.ger.corp.intel.com) ([10.249.35.133]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 03:51:45 -0700 From: Peter Ujfalusi To: lgirdwood@gmail.com, broonie@kernel.org Cc: linux-sound@vger.kernel.org, pierre-louis.bossart@linux.intel.com, kai.vehmanen@linux.intel.com, ranjani.sridharan@linux.intel.com, rander.wang@intel.com, liam.r.girdwood@intel.com Subject: [PATCH 2/7] ASoC: SOF: Intel: mtl: Correct rom_status_reg Date: Wed, 3 Apr 2024 13:52:05 +0300 Message-ID: <20240403105210.17949-3-peter.ujfalusi@linux.intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240403105210.17949-1-peter.ujfalusi@linux.intel.com> References: <20240403105210.17949-1-peter.ujfalusi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 ACE1 architecture changed the place where the ROM updates the status code from the shared SRAM window to HFFLGP1QW0 register for the status and HFFLGP1QW0 + 4 for the error code. The rom_status_reg is not used on MTL because it was wrongly assigned based on older platform convention (SRAM window) and it was giving inconsistent readings. Fixes: 064520e8aeaa ("ASoC: SOF: Intel: Add support for MeteorLake (MTL)") Signed-off-by: Peter Ujfalusi Reviewed-by: Rander Wang Reviewed-by: Kai Vehmanen Reviewed-by: Pierre-Louis Bossart Reviewed-by: Liam Girdwood --- sound/soc/sof/intel/mtl.c | 4 ++-- sound/soc/sof/intel/mtl.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/sound/soc/sof/intel/mtl.c b/sound/soc/sof/intel/mtl.c index c640fbf6615a..a27ce8debe91 100644 --- a/sound/soc/sof/intel/mtl.c +++ b/sound/soc/sof/intel/mtl.c @@ -732,7 +732,7 @@ const struct sof_intel_dsp_desc mtl_chip_info = { .ipc_ack = MTL_DSP_REG_HFIPCXIDA, .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, - .rom_status_reg = MTL_DSP_ROM_STS, + .rom_status_reg = MTL_DSP_REG_HFFLGPXQWY, .rom_init_timeout = 300, .ssp_count = MTL_SSP_COUNT, .ssp_base_offset = CNL_SSP_BASE_OFFSET, @@ -760,7 +760,7 @@ const struct sof_intel_dsp_desc arl_s_chip_info = { .ipc_ack = MTL_DSP_REG_HFIPCXIDA, .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, - .rom_status_reg = MTL_DSP_ROM_STS, + .rom_status_reg = MTL_DSP_REG_HFFLGPXQWY, .rom_init_timeout = 300, .ssp_count = MTL_SSP_COUNT, .ssp_base_offset = CNL_SSP_BASE_OFFSET, diff --git a/sound/soc/sof/intel/mtl.h b/sound/soc/sof/intel/mtl.h index ea8c1b83f712..3c56427a966b 100644 --- a/sound/soc/sof/intel/mtl.h +++ b/sound/soc/sof/intel/mtl.h @@ -70,8 +70,8 @@ #define MTL_DSP_ROM_STS MTL_SRAM_WINDOW_OFFSET(0) /* ROM status */ #define MTL_DSP_ROM_ERROR (MTL_SRAM_WINDOW_OFFSET(0) + 0x4) /* ROM error code */ -#define MTL_DSP_REG_HFFLGPXQWY 0x163200 /* ROM debug status */ -#define MTL_DSP_REG_HFFLGPXQWY_ERROR 0x163204 /* ROM debug error code */ +#define MTL_DSP_REG_HFFLGPXQWY 0x163200 /* DSP core0 status */ +#define MTL_DSP_REG_HFFLGPXQWY_ERROR 0x163204 /* DSP core0 error */ #define MTL_DSP_REG_HfIMRIS1 0x162088 #define MTL_DSP_REG_HfIMRIS1_IU_MASK BIT(0)