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Mon, 11 Nov 2024 18:53:14 -0800 (PST) Received: from localhost.localdomain ([2.222.231.247]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381ed999e0csm14056380f8f.59.2024.11.11.18.53.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Nov 2024 18:53:13 -0800 (PST) From: Alexey Klimov To: andersson@kernel.org, konradybcio@kernel.org, linux-arm-msm@vger.kernel.org Cc: linux-sound@vger.kernel.org, srinivas.kandagatla@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, krzysztof.kozlowski@linaro.org, caleb.connolly@linaro.org, a39.skl@gmail.com, konrad.dybcio@oss.qualcomm.com, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/4] arm64: dts: qcom: sm4250: add LPASS LPI pin controller Date: Tue, 12 Nov 2024 02:53:05 +0000 Message-ID: <20241112025306.712122-4-alexey.klimov@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241112025306.712122-1-alexey.klimov@linaro.org> References: <20241112025306.712122-1-alexey.klimov@linaro.org> Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin controller device node required for audio subsystem on Qualcomm QRB4210 RB2. QRB4210 is based on sm4250 which has a slightly different lpass pin controller comparing to sm6115. While at this, also add description of lpi_i2s2 pins (active state) required for audio playback via HDMI. Cc: Srinivas Kandagatla Reviewed-by: Dmitry Baryshkov Signed-off-by: Alexey Klimov --- arch/arm64/boot/dts/qcom/sm4250.dtsi | 39 ++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm4250.dtsi b/arch/arm64/boot/dts/qcom/sm4250.dtsi index a0ed61925e12..cd8c8e59976e 100644 --- a/arch/arm64/boot/dts/qcom/sm4250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4250.dtsi @@ -36,3 +36,42 @@ &cpu6 { &cpu7 { compatible = "qcom,kryo240"; }; + +&lpass_tlmm { + compatible = "qcom,sm4250-lpass-lpi-pinctrl"; + gpio-ranges = <&lpass_tlmm 0 0 27>; + + lpi_i2s2_active: lpi-i2s2-active-state { + sck-pins { + pins = "gpio10"; + function = "i2s2_clk"; + bias-disable; + drive-strength = <8>; + output-high; + }; + + ws-pins { + pins = "gpio11"; + function = "i2s2_ws"; + bias-disable; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio12"; + function = "i2s2_data"; + bias-disable; + drive-strength = <8>; + output-high; + }; + + ext-mclk1-pins { + pins = "gpio18"; + function = "ext_mclk1_a"; + bias-disable; + drive-strength = <16>; + output-high; + }; + }; +};