From patchwork Thu Dec 26 16:22:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13921341 Received: from mx.denx.de (mx.denx.de [89.58.32.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91A3684D3E; Thu, 26 Dec 2024 16:22:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=89.58.32.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735230178; cv=none; b=Y2QNAwR9i4+HDhRXmA7DaqRm3L8wsRIcOhz7fQKo0IE4XdgeERb/Eco062GIAlmg625gTb6/fgNCGwoBNUqYwSwlwyxd0nRbMoeyL0BTXf++FN91k+okEXM7EtOZ9uBd5+qXJgZm3XkkwCcwrS2Ok+JH21QyndxnC39ECH8GBF4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735230178; c=relaxed/simple; bh=5aCbI2K427pdBykH0gN4I6znnRQi37S6u7WxqV2eLZE=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=bXXzbjZNnIQ7d0B3oiVQY8iFrZA53pHuw5Av4mjhJTYxQIwpOPRGQ6RZHvp5ObhNnfX/DHLfnQ03ULtI8Z+fIZXV99CotCwiHwZqEabIMXEBcmF/FpkUXMFCHIsTQ/2UdZQhXj2dRe9XWIIT1z9mAZ0/NoQKZVk60wArsGsQNIw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de; spf=pass smtp.mailfrom=denx.de; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b=O9crRWSy; arc=none smtp.client-ip=89.58.32.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=denx.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b="O9crRWSy" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id EAEBF1040DBCD; Thu, 26 Dec 2024 17:22:51 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1735230173; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=qqyvmTjSiY+9V+RBa890QnBjvcMSQnicH+IEIShh81I=; b=O9crRWSy9SAY//tNpjJL1x1/369KyIjzL76Cn7SL68uhZlaIs/nxjU5Z839TV6G9jNjGMv M2tHBRznXtFKoDPDXvmvB7vXSHhYp1/oe/4ob4AewyB0KfwoZz1kVcinwDQah3kfg5nr4L 70/NMTC6lG3x5nsi4PZUC4v/P97xdTsYBdTBzUqFgQY1h4+WEsPoI25Wji0AAntuGUz7el lfg4Bm7DkyLfCAqQGQeEkw4AT4mzgahKWjSvY13dFSx93NkKBP8ErGri3DtPUeNc/A88NQ 67NJ/B7ko/2FWXP1epYIIDiitzB+wcK1Fcfzxw85lFgxTeoMe4JzBR+iAw4lnQ== From: Marek Vasut To: linux-clk@vger.kernel.org Cc: Marek Vasut , Conor Dooley , Fabio Estevam , Jaroslav Kysela , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Michael Turquette , Michael Walle , Nicolin Chen , Rob Herring , Shengjiu Wang , Stephen Boyd , Takashi Iwai , Xiubo Li , devicetree@vger.kernel.org, linux-sound@vger.kernel.org Subject: [PATCH v2 1/4] dt-bindings: clock: fsl-sai: Document i.MX8M support Date: Thu, 26 Dec 2024 17:22:21 +0100 Message-ID: <20241226162234.40141-1-marex@denx.de> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 The i.MX8M/Mini/Nano/Plus variant of the SAI IP has control registers shifted by +8 bytes and requires additional bus clock. Document support for the i.MX8M variant of the IP with this register shift and additional clock. Update the description slightly. Signed-off-by: Marek Vasut Acked-by: Conor Dooley --- Cc: Conor Dooley Cc: Fabio Estevam Cc: Jaroslav Kysela Cc: Krzysztof Kozlowski Cc: Liam Girdwood Cc: Mark Brown Cc: Michael Turquette Cc: Michael Walle Cc: Nicolin Chen Cc: Rob Herring Cc: Shengjiu Wang Cc: Stephen Boyd Cc: Takashi Iwai Cc: Xiubo Li Cc: devicetree@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-sound@vger.kernel.org --- V2: No change --- .../bindings/clock/fsl,sai-clock.yaml | 32 ++++++++++++++++--- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml index 3bca9d11c148f..e62543deeb7da 100644 --- a/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml +++ b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml @@ -10,10 +10,10 @@ maintainers: - Michael Walle description: | - It is possible to use the BCLK pin of a SAI module as a generic clock - output. Some SoC are very constrained in their pin multiplexer - configuration. Eg. pins can only be changed groups. For example, on the - LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI, + It is possible to use the BCLK pin of a SAI module as a generic + clock output. Some SoC are very constrained in their pin multiplexer + configuration. E.g. pins can only be changed in groups. For example, on + the LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI, the second pins are wasted. Using this binding it is possible to use the clock of the second SAI as a MCLK clock for an audio codec, for example. @@ -21,7 +21,17 @@ description: | properties: compatible: - const: fsl,vf610-sai-clock + oneOf: + - items: + - enum: + - fsl,imx8mm-sai-clock + - fsl,imx8mn-sai-clock + - fsl,imx8mp-sai-clock + - const: fsl,imx8mq-sai-clock + - items: + - enum: + - fsl,imx8mq-sai-clock + - fsl,vf610-sai-clock reg: maxItems: 1 @@ -32,6 +42,18 @@ properties: '#clock-cells': const: 0 +allOf: + - if: + not: + properties: + compatible: + contains: + const: fsl,imx8mq-sai-clock + then: + properties: + clocks: + maxItems: 2 + required: - compatible - reg