From patchwork Wed Jul 2 14:44:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lin, Mengdong" X-Patchwork-Id: 4465941 X-Patchwork-Delegate: tiwai@suse.de Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 67150BEEAA for ; Wed, 2 Jul 2014 14:43:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8A04820304 for ; Wed, 2 Jul 2014 14:43:07 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 42D0420204 for ; Wed, 2 Jul 2014 14:43:06 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 567D3265832; Wed, 2 Jul 2014 16:43:05 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,NO_DNS_FOR_FROM, UNPARSEABLE_RELAY autolearn=no version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id 877642657D8; Wed, 2 Jul 2014 16:41:46 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 4ABF2265801; Wed, 2 Jul 2014 16:41:45 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by alsa0.perex.cz (Postfix) with ESMTP id BDDB62652F1 for ; Wed, 2 Jul 2014 16:41:37 +0200 (CEST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 02 Jul 2014 07:36:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.01,588,1400050800"; d="scan'208";a="567298015" Received: from amanda-hsw-pc.sh.intel.com ([10.239.37.27]) by orsmga002.jf.intel.com with ESMTP; 02 Jul 2014 07:41:07 -0700 From: mengdong.lin@intel.com To: alsa-devel@alsa-project.org, tiwai@suse.de, jani.nikula@intel.com Date: Wed, 2 Jul 2014 22:44:07 +0800 Message-Id: <54aede59c2ab488ffff3c92c45798efb38a5e0d2.1404311751.git.mengdong.lin@intel.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: References: Cc: Mengdong Lin Subject: [alsa-devel] [PATCH 3/3] ALSA: hda - restore BCLK M/N value as per CDCLK for HSW/BDW display HDA controller X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mengdong Lin For HSW/BDW display HD-A controller, this patch restores BCLK by setting the M/N values as per the core display clock (CDCLK) queried from i915 display driver. And the audio driver will also restore BCLK in azx_first_init() since the display driver can turn off the shared power in boot phase if only eDP is connected and M/N values will be lost and must be reprogrammed. Signed-off-by: Mengdong Lin diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index 25753db..c7dfd1d 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -299,10 +299,6 @@ static char *driver_short_names[] = { struct hda_intel { struct azx chip; - - /* HSW/BDW display HDA controller to restore BCLK from CDCLK */ - unsigned int bclk_m; - unsigned int bclk_n; }; @@ -598,20 +594,41 @@ static int param_set_xint(const char *val, const struct kernel_param *kp) #define azx_del_card_list(chip) /* NOP */ #endif /* CONFIG_PM */ -static void haswell_save_bclk(struct azx *chip) -{ - struct hda_intel *hda = container_of(chip, struct hda_intel, chip); - - hda->bclk_m = azx_readw(chip, EM4); - hda->bclk_n = azx_readw(chip, EM5); -} static void haswell_restore_bclk(struct azx *chip) { - struct hda_intel *hda = container_of(chip, struct hda_intel, chip); + int cdclk_freq; + unsigned int bclk_m, bclk_n; + + cdclk_freq = hda_get_display_clk(); + switch (cdclk_freq) { + case 337500: + bclk_m = 16; + bclk_n = 225; + break; + + case 450000: /* default CDCLK 450MHz */ + bclk_m = 4; + bclk_n = 75; + break; + + case 540000: + bclk_m = 4; + bclk_n = 90; + break; + + case 675000: + bclk_m = 8; + bclk_n = 225; + break; - azx_writew(chip, EM4, hda->bclk_m); - azx_writew(chip, EM5, hda->bclk_n); + default: + bclk_m = 4; + bclk_n = 75; + } + + azx_writew(chip, EM4, bclk_m); + azx_writew(chip, EM5, bclk_n); } #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO) @@ -641,12 +658,6 @@ static int azx_suspend(struct device *dev) chip->irq = -1; } - /* Save BCLK M/N values before they become invalid in D3. - * Will test if display power well can be released now. - */ - if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) - haswell_save_bclk(chip); - if (chip->msi) pci_disable_msi(chip->pci); pci_disable_device(pci); @@ -713,10 +724,9 @@ static int azx_runtime_suspend(struct device *dev) azx_stop_chip(chip); azx_enter_link_reset(chip); azx_clear_irq_pending(chip); - if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { - haswell_save_bclk(chip); + if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) hda_display_power(false); - } + return 0; } @@ -1426,6 +1436,10 @@ static int azx_first_init(struct azx *chip) /* initialize chip */ azx_init_pci(chip); + + if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) + haswell_restore_bclk(chip); + azx_init_chip(chip, (probe_only[dev] & 2) == 0); /* codec detection */