From patchwork Tue Apr 1 11:52:52 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 3921151 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id ABE4E9F2B6 for ; Tue, 1 Apr 2014 11:53:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C1A28203B6 for ; Tue, 1 Apr 2014 11:53:22 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 402DD20221 for ; Tue, 1 Apr 2014 11:53:21 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id C5560265361; Tue, 1 Apr 2014 13:53:19 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Status: No, score=-0.6 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY, UNRESOLVED_TEMPLATE autolearn=no version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id 481E42652EE; Tue, 1 Apr 2014 13:53:08 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 48D332652EE; Tue, 1 Apr 2014 13:53:07 +0200 (CEST) Received: from am1outboundpool.messaging.microsoft.com (am1ehsobe001.messaging.microsoft.com [213.199.154.204]) by alsa0.perex.cz (Postfix) with ESMTP id C5E2F2652C2 for ; Tue, 1 Apr 2014 13:52:58 +0200 (CEST) Received: from mail96-am1-R.bigfish.com (10.3.201.246) by AM1EHSOBE014.bigfish.com (10.3.207.136) with Microsoft SMTP Server id 14.1.225.22; Tue, 1 Apr 2014 11:52:58 +0000 Received: from mail96-am1 (localhost [127.0.0.1]) by mail96-am1-R.bigfish.com (Postfix) with ESMTP id CB894120205; Tue, 1 Apr 2014 11:52:57 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah21bch1fc6hzz1de098h8275bh1de097hz2dh2a8h839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h24afh2327h2336h2438h2461h2487h24d7h2516h2545h255eh25cch25f6h2605h268bh1155h) Received: from mail96-am1 (localhost.localdomain [127.0.0.1]) by mail96-am1 (MessageSwitch) id 1396353175223844_4075; Tue, 1 Apr 2014 11:52:55 +0000 (UTC) Received: from AM1EHSMHS021.bigfish.com (unknown [10.3.201.254]) by mail96-am1.bigfish.com (Postfix) with ESMTP id 2A5B23A008C; Tue, 1 Apr 2014 11:52:55 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by AM1EHSMHS021.bigfish.com (10.3.207.150) with Microsoft SMTP Server (TLS) id 14.16.227.3; Tue, 1 Apr 2014 11:52:54 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.3.158.2; Tue, 1 Apr 2014 11:52:53 +0000 Received: from rio.ap.freescale.net (rio.ap.freescale.net [10.192.242.9]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s31Bqf5j008212; Tue, 1 Apr 2014 04:52:49 -0700 From: Nicolin Chen To: , Date: Tue, 1 Apr 2014 19:52:52 +0800 Message-ID: <87d225a25812d730c0865f9d0bb733c67d8b3ed1.1396352401.git.Guangyu.Chen@freescale.com> X-Mailer: git-send-email 1.8.4 In-Reply-To: References: MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-FOPE-CONNECTOR: Id%0$Dn%FREESCALE.MAIL.ONMICROSOFT.COM$RO%1$TLS%0$FQDN%$TlsDn% Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, alsa-devel@alsa-project.org, pawel.moll@arm.com, linux-doc@vger.kernel.org, ijc+devicetree@hellion.org.uk, linux-kernel@vger.kernel.org, robh+dt@kernel.org, timur@tabi.org, Li.Xiubo@freescale.com, rob@landley.net, galak@codeaurora.org, linuxppc-dev@lists.ozlabs.org Subject: [alsa-devel] [PATCH 1/2] ASoC: fsl_sai: Add clock control for SAI X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP The SAI mainly has two clocks: ipg_clock -- registers access for SoC or DMA to read and write. sai_clock -- providing DAI format bit clock and frame clock. Thus this patch adds these two clocks to the driver with their clock controls and replaces the regmap clock 'sai_clock' with 'ipg_clock'. Signed-off-by: Nicolin Chen Acked-by: Xiubo Li --- .../devicetree/bindings/sound/fsl-sai.txt | 7 ++-- sound/soc/fsl/fsl_sai.c | 37 ++++++++++++++++++++-- sound/soc/fsl/fsl_sai.h | 2 ++ 3 files changed, 41 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 35c09fe..bad4453 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -11,5 +11,6 @@ Required properties: - reg: Offset and length of the register set for the device. - clocks: Must contain an entry for each entry in clock-names. -- clock-names : Must include the "sai" entry. +- clock-names : Must include the "ipg" for register access and "sai" for bit + clock and frame clock providing. - dmas : Generic dma devicetree binding as described in Documentation/devicetree/bindings/dma/dma.txt. @@ -31,6 +32,6 @@ sai2: sai@40031000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai2_1>; - clocks = <&clks VF610_CLK_SAI2>; - clock-names = "sai"; + clocks = <&clks VF610_CLK_SAI2>, <&clks VF610_CLK_SAI2>; + clock-names = "ipg", "sai"; dma-names = "tx", "rx"; dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>, diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 3847d2a..2d749df 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -428,5 +428,18 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream, { struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); - u32 reg; + struct device *dev = &sai->pdev->dev; + u32 reg, ret; + + ret = clk_prepare_enable(sai->ipg_clk); + if (ret) { + dev_err(dev, "failed to prepare and enable ipg clock\n"); + return ret; + } + + ret = clk_prepare_enable(sai->sai_clk); + if (ret) { + dev_err(dev, "failed to prepare and enable sai clock\n"); + goto err; + } if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) @@ -439,4 +452,9 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream, return 0; + +err: + clk_disable_unprepare(sai->ipg_clk); + + return ret; } @@ -454,4 +472,7 @@ static void fsl_sai_shutdown(struct snd_pcm_substream *substream, regmap_update_bits(sai->regmap, reg, FSL_SAI_CR3_TRCE, ~FSL_SAI_CR3_TRCE); + + clk_disable_unprepare(sai->sai_clk); + clk_disable_unprepare(sai->ipg_clk); } @@ -609,5 +630,5 @@ static int fsl_sai_probe(struct platform_device *pdev) sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, - "sai", base, &fsl_sai_regmap_config); + "ipg", base, &fsl_sai_regmap_config); if (IS_ERR(sai->regmap)) { dev_err(&pdev->dev, "regmap init failed\n"); @@ -615,4 +636,16 @@ static int fsl_sai_probe(struct platform_device *pdev) } + sai->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); + if (IS_ERR(sai->ipg_clk)) { + dev_err(&pdev->dev, "failed to get ipg clock\n"); + return PTR_ERR(sai->ipg_clk); + } + + sai->sai_clk = devm_clk_get(&pdev->dev, "sai"); + if (IS_ERR(sai->sai_clk)) { + dev_err(&pdev->dev, "failed to get sai clock\n"); + return PTR_ERR(sai->sai_clk); + } + irq = platform_get_irq(pdev, 0); if (irq < 0) { diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 677670d..cbaf114 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -127,4 +127,6 @@ struct fsl_sai { struct platform_device *pdev; struct regmap *regmap; + struct clk *ipg_clk; + struct clk *sai_clk; bool big_endian_regs;