From patchwork Tue Sep 1 01:27:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Albert Chen X-Patchwork-Id: 7105491 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4851E9F32B for ; Tue, 1 Sep 2015 14:09:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A03F8205F9 for ; Tue, 1 Sep 2015 14:09:40 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 01E72205E2 for ; Tue, 1 Sep 2015 14:09:39 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 112C62651AC; Tue, 1 Sep 2015 16:09:37 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id E0C652604F8; Tue, 1 Sep 2015 16:09:26 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id B7F21261A1A; Tue, 1 Sep 2015 03:27:42 +0200 (CEST) Received: from rtits2.realtek.com.tw (rtits2.realtek.com [60.250.210.242]) by alsa0.perex.cz (Postfix) with ESMTP id 96F332616F3 for ; Tue, 1 Sep 2015 03:27:35 +0200 (CEST) Authenticated-By: X-SpamFilter-By: BOX Solutions SpamTrap 5.54 with qID t811RQ1K004833, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtitcas12.realtek.com.tw[172.21.6.16]) by rtits2.realtek.com.tw (8.14.9/2.40/5.66) with ESMTP id t811RQ1K004833 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NOT); Tue, 1 Sep 2015 09:27:28 +0800 Received: from RTITCASV02.realtek.com.tw (172.21.6.19) by RTITCAS12.realtek.com.tw (172.21.6.16) with Microsoft SMTP Server (TLS) id 14.3.224.2; Tue, 1 Sep 2015 09:27:28 +0800 Received: from RTITMBSV05.realtek.com.tw ([fe80::c054:8e59:cadd:4c42]) by RTITCASV02.realtek.com.tw ([::1]) with mapi id 14.03.0248.002; Tue, 1 Sep 2015 09:27:27 +0800 From: Albert Chen To: Anatol Pomozov , "alsa-devel@alsa-project.org" Thread-Topic: [PATCH] ASoC: Document DAI signal polarity Thread-Index: AQHQ5C7DW5rdoZBZMEWxSMUseczLpZ4m4k+w Date: Tue, 1 Sep 2015 01:27:26 +0000 Message-ID: <9EE27E29D4384141AEEB23E69581718501431DDB@RTITMBSV05.realtek.com.tw> References: <1441054258-33200-1-git-send-email-anatol.pomozov@gmail.com> In-Reply-To: <1441054258-33200-1-git-send-email-anatol.pomozov@gmail.com> Accept-Language: zh-TW, en-US Content-Language: zh-TW X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.21.82.150] MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 01 Sep 2015 16:09:26 +0200 Cc: "liam.r.girdwood@linux.intel.com" , Bard Liao , Oder Chiou , "broonie@kernel.org" , "lars@metafoo.de" Subject: Re: [alsa-devel] [PATCH] ASoC: Document DAI signal polarity X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP Loop more -----Original Message----- From: Anatol Pomozov [mailto:anatol.pomozov@gmail.com] Sent: Tuesday, September 01, 2015 4:51 AM To: alsa-devel@alsa-project.org Cc: broonie@kernel.org; lars@metafoo.de; Albert Chen; liam.r.girdwood@linux.intel.com; Anatol Pomozov Subject: [PATCH] ASoC: Document DAI signal polarity Per discussion at [1] currently there is no clear definition of what is FSYNC polarity. Different drivers use its own definition of what is "normal" and what is "inverted" fsync in different modes. This leads to compatibility problems between drivers. Explicitly specify meaning of BCLK/FSYNC polarity. [1] http://mailman.alsa-project.org/pipermail/alsa-devel/2015-August/097121.html Signed-off-by: Anatol Pomozov --- include/sound/soc-dai.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) -- 2.5.0.457.gab17608 ------Please consider the environment before printing this e-mail. diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h index 2df96b1..c8170c4 100644 --- a/include/sound/soc-dai.h +++ b/include/sound/soc-dai.h @@ -48,10 +48,15 @@ struct snd_compr_stream; #define SND_SOC_DAIFMT_GATED (0 << 4) /* clock is gated */ /* - * DAI hardware signal inversions. + * DAI hardware signal polarity. * - * Specifies whether the DAI can also support inverted clocks for the specified - * format. + * For BCLK: + * - "normal" polarity means signal sensing happens at rising edge of + BCLK + * - "inverted" polarity means signal sensing happens at falling edge + of BCLK + * + * For FSYNC: + * - "normal" polarity means frame starts at rising edge of FSYNC + * - "inverted" polarity means frame starts at falling edge of FSYNC */ #define SND_SOC_DAIFMT_NB_NF (0 << 8) /* normal bit clock + frame */ #define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */