iMX6UL EVK with kernel 4.6

Commit Message

Fabio Estevam May 2, 2016, 1:17 p.m. UTC

Hi Petr,

On Mon, May 2, 2016 at 9:43 AM, Fabio Estevam <[e-mail]> wrote:

> Ok, managed to unmute these options in alsamixer and now I get audio
> with NXP 3.14 kernel.
>
> Will try with mainline now.

I can get audio with mainline now, but it plays with an incorrect pitch.

Here is a quick hack to allow MCLK to be driven:

As next steps we need:

1. Fix the sound pitch

2. Find a proper way to enable MCLK.

Let me know if you get any progress so that we can upstream audio on this board.

Comments

Petr Kulhavy May 2, 2016, 7:30 p.m. UTC | #1

Hi Fabio,

On 02/05/16 15:17, Fabio Estevam wrote:
> Hi Petr,
>
> I can get audio with mainline now, but it plays with an incorrect pitch.
>
> Here is a quick hack to allow MCLK to be driven:
>
> --- a/arch/arm/mach-imx/mach-imx6ul.c
> +++ b/arch/arm/mach-imx/mach-imx6ul.c
> @@ -22,9 +22,12 @@ static void __init imx6ul_enet_clk_init(void)
>          struct regmap *gpr;
>
>          gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
> -       if (!IS_ERR(gpr))
> +       if (!IS_ERR(gpr)) {
>                  regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR,
>                                     IMX6UL_GPR1_ENET_CLK_OUTPUT);
> +               regmap_update_bits(gpr, IOMUXC_GPR1, (1 << 20), (1 << 20));
> +
> +       }
>          else
>                  pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");
Cool, now my board plays too! Thanks!
> As next steps we need:
>
> 1. Fix the sound pitch
Mine plays at the correct speed. For the correct speed the clock 
assignment from the Freescale DTS needs to be copied, so that the SAI2 
clock generates 12.288MHz.
Below are the relevant nodes from my DTS:

&clks {
         assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
         assigned-clock-rates = <786432000>;
};

&sai2 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_sai2>;

         assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
                           <&clks IMX6UL_CLK_SAI2>;
         assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
         assigned-clock-rates = <0>, <12288000>;

         status = "okay";
};

> 2. Find a proper way to enable MCLK.
>

I would tend to put the control of the SAIx_MCLK_DIR into the SAI driver 
and if needed add an extra boolean property like "enable-mclk-output".
Leaving it independent makes not much sense, for binding to the 
clock/pinmux it's too generic and the Freescale solution with a gpr phandle
isn't very lucky either as it forces the use of the fsl soundcard and 
doesn't allow e.g. the simple-audio-card.

But let's see what else the Freescale or ALSA developers suggest.

Cheers
Petr

Fabio Estevam May 2, 2016, 7:53 p.m. UTC | #2

On Mon, May 2, 2016 at 4:30 PM, Petr Kulhavy <[e-mail]> wrote:

> Mine plays at the correct speed. For the correct speed the clock assignment
> from the Freescale DTS needs to be copied, so that the SAI2 clock generates
> 12.288MHz.
> Below are the relevant nodes from my DTS:
>
> &clks {
>         assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
>         assigned-clock-rates = <786432000>;
> };

That was the part I was missing, thanks!

It plays correctly now, but I get this error message from the wm8960 driver:

$ aplay /home/clarinet.wav
[   55.007221] wm8960 1-001a: failed to configure clock
[   55.012583] wm8960 1-001a: ASoC: Failed to prepare bias: -22

Do you see this too?

>> 2. Find a proper way to enable MCLK.
>>
>
> I would tend to put the control of the SAIx_MCLK_DIR into the SAI driver and
> if needed add an extra boolean property like "enable-mclk-output".

Yes, I think this makes sense.

I will propose some patches today or tomorrow and will keep you on Cc.

Thanks for the cooperation :-)

Patch

--- a/arch/arm/mach-imx/mach-imx6ul.c
+++ b/arch/arm/mach-imx/mach-imx6ul.c
@@ -22,9 +22,12 @@  static void __init imx6ul_enet_clk_init(void)
        struct regmap *gpr;

        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
-       if (!IS_ERR(gpr))
+       if (!IS_ERR(gpr)) {
                regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR,
                                   IMX6UL_GPR1_ENET_CLK_OUTPUT);
+               regmap_update_bits(gpr, IOMUXC_GPR1, (1 << 20), (1 << 20));
+
+       }
        else
                pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");