From patchwork Thu Apr 23 13:16:05 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyri Sarha X-Patchwork-Id: 6262491 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0C8ACBF4A6 for ; Thu, 23 Apr 2015 13:18:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 20F9E2035B for ; Thu, 23 Apr 2015 13:18:08 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id D86952026F for ; Thu, 23 Apr 2015 13:18:03 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 09C1C26663F; Thu, 23 Apr 2015 15:18:02 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id 97AEC265091; Thu, 23 Apr 2015 15:16:34 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id DB3B5265091; Thu, 23 Apr 2015 15:16:31 +0200 (CEST) Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by alsa0.perex.cz (Postfix) with ESMTP id 5081E261AF0 for ; Thu, 23 Apr 2015 15:16:24 +0200 (CEST) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id t3NDGI8b011365; Thu, 23 Apr 2015 08:16:18 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t3NDGH59026322; Thu, 23 Apr 2015 08:16:17 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.224.2; Thu, 23 Apr 2015 08:16:17 -0500 Received: from imryr.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id t3NDGCW9022174; Thu, 23 Apr 2015 08:16:16 -0500 From: Jyri Sarha To: Date: Thu, 23 Apr 2015 16:16:05 +0300 Message-ID: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: MIME-Version: 1.0 Cc: peter.ujfalusi@ti.com, liam.r.girdwood@linux.intel.com, broonie@kernel.org, Jyri Sarha Subject: [alsa-devel] [PATCH v2 2/3] ASoC: davinci-mcasp: Channel count constraints for multi-serializer case X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP Set channel count constraints for multiple serializers case. On McASP the active channels mask is the same for all the serializers. With the current implementation this means that if more than one serializers is used, all TDM slots have to be active on all serializers. The patch sets the channel count constraints according to number of RX and TX serializers. Reported-by: Misael Lopez Cruz Signed-off-by: Jyri Sarha --- sound/soc/davinci/davinci-mcasp.c | 63 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c index a01c6db..f841707 100644 --- a/sound/soc/davinci/davinci-mcasp.c +++ b/sound/soc/davinci/davinci-mcasp.c @@ -107,6 +107,7 @@ struct davinci_mcasp { #endif struct davinci_mcasp_ruledata ruledata[2]; + struct snd_pcm_hw_constraint_list chconstr[2]; }; static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, @@ -1119,6 +1120,11 @@ static int davinci_mcasp_startup(struct snd_pcm_substream *substream, SNDRV_PCM_HW_PARAM_CHANNELS, 2, max_channels); + if (mcasp->chconstr[substream->stream].count) + snd_pcm_hw_constraint_list(substream->runtime, + 0, SNDRV_PCM_HW_PARAM_CHANNELS, + &mcasp->chconstr[substream->stream]); + /* * If we rely on implicit BCLK divider setting we should * set constraints based on what we can provide. @@ -1498,6 +1504,59 @@ nodata: return pdata; } +/* All serializers must have equal number of channels */ +static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, + struct snd_pcm_hw_constraint_list *cl, + int serializers) +{ + unsigned int *list; + int i, count = 0; + + if (serializers <= 1) + return 0; + + list = devm_kzalloc(mcasp->dev, sizeof(unsigned int) * + (mcasp->tdm_slots + serializers - 2), + GFP_KERNEL); + if (!list) + return -ENOMEM; + + for (i = 2; i <= mcasp->tdm_slots; i++) + list[count++] = i; + + for (i = 2; i <= serializers; i++) + list[count++] = i*mcasp->tdm_slots; + + cl->count = count; + cl->list = list; + + return 0; +} + + +static int davinci_mcasp_init_ch_constraints(struct davinci_mcasp *mcasp) +{ + int rx_serializers = 0, tx_serializers = 0, ret, i; + + for (i = 0; i < mcasp->num_serializer; i++) + if (mcasp->serial_dir[i] == TX_MODE) + tx_serializers++; + else if (mcasp->serial_dir[i] == RX_MODE) + rx_serializers++; + + ret = davinci_mcasp_ch_constraint(mcasp, &mcasp->chconstr[ + SNDRV_PCM_STREAM_PLAYBACK], + tx_serializers); + if (ret) + return ret; + + ret = davinci_mcasp_ch_constraint(mcasp, &mcasp->chconstr[ + SNDRV_PCM_STREAM_CAPTURE], + rx_serializers); + + return ret; +} + static int davinci_mcasp_probe(struct platform_device *pdev) { struct snd_dmaengine_dai_dma_data *dma_data; @@ -1681,6 +1740,10 @@ static int davinci_mcasp_probe(struct platform_device *pdev) mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; } + ret = davinci_mcasp_init_ch_constraints(mcasp); + if (ret) + goto err; + dev_set_drvdata(&pdev->dev, mcasp); mcasp_reparent_fck(pdev);