From patchwork Wed May 4 17:08:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charles Keepax X-Patchwork-Id: 12838350 Received: from mx0b-001ae601.pphosted.com (mx0b-001ae601.pphosted.com [67.231.152.168]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B905F29AA for ; Wed, 4 May 2022 18:24:09 +0000 (UTC) Received: from pps.filterd (m0077474.ppops.net [127.0.0.1]) by mx0b-001ae601.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2446EsA7021058; Wed, 4 May 2022 12:09:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=By/S9E1F2xzDnQr0GMOU8svqtPkdMZwDtBOpCYX22YI=; b=P5axK1PJRRmMLXiLDuM5I6/QF6U6cU96q/UggEL7PNf+JXq/3R/JdLewpNvarZhPRXbY 3sJkC0+bDBzlZMFd67dM7I4GcpmZ7BB5zrTlrAspn5Sg3HdppL1GJ8X4wpCwDC7qgxdS fc5FCAtUlfsvjsDRX+88Nvj7qaaozd1HB76/soHKqCNaH4EQRIHmFJ+pDWZT9eY+StZR xmbJgpzua6qj2rAkYH20G9x2s7Z0LCvlW1vgaEsccbX7epKHenM4c0qrXIv7ie/JHNjB Re4ERFHsvkTFLsNhuvn0PzidrqJtNXEKklUEbeoIXR0ycF116pBGwp24bMtYdYuWYcgn TA== Received: from ediex01.ad.cirrus.com ([84.19.233.68]) by mx0b-001ae601.pphosted.com (PPS) with ESMTPS id 3fs1hpcxs0-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Wed, 04 May 2022 12:09:10 -0500 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Wed, 4 May 2022 18:09:05 +0100 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.24 via Frontend Transport; Wed, 4 May 2022 18:09:05 +0100 Received: from algalon.ad.cirrus.com (algalon.ad.cirrus.com [198.90.251.122]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 6DA35B10; Wed, 4 May 2022 17:09:05 +0000 (UTC) From: Charles Keepax To: CC: , , , , , , , , , , , , , , , , , Subject: [PATCH 04/38] ASoC: cs4270: Remove redundant big endian formats Date: Wed, 4 May 2022 18:08:31 +0100 Message-ID: <20220504170905.332415-5-ckeepax@opensource.cirrus.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220504170905.332415-1-ckeepax@opensource.cirrus.com> References: <20220504170905.332415-1-ckeepax@opensource.cirrus.com> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: w8jsU8o_xUE6YpioPdqlGirmYJgEPoSv X-Proofpoint-GUID: w8jsU8o_xUE6YpioPdqlGirmYJgEPoSv X-Proofpoint-Spam-Reason: safe The CODEC already provides the endianness flag on its snd_soc_component_driver structure, specifying it is ambivalent to endian. The core will expand the formats to cover both endian types, as such remove the redundant specification of both endians. Signed-off-by: Charles Keepax --- sound/soc/codecs/cs4270.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/sound/soc/codecs/cs4270.c b/sound/soc/codecs/cs4270.c index 07cac01f87bdc..531f63b015547 100644 --- a/sound/soc/codecs/cs4270.c +++ b/sound/soc/codecs/cs4270.c @@ -32,18 +32,9 @@ #include #include -/* - * The codec isn't really big-endian or little-endian, since the I2S - * interface requires data to be sent serially with the MSbit first. - * However, to support BE and LE I2S devices, we specify both here. That - * way, ALSA will always match the bit patterns. - */ -#define CS4270_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ - SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \ - SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \ - SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE | \ - SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE | \ - SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE) +#define CS4270_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) /* CS4270 registers addresses */ #define CS4270_CHIPID 0x01 /* Chip ID */