| Message ID | 20240108181612.5651-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add support for Renesas RZ/Five RISC-V SoC | expand |
Hi! > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as > entry-class social infrastructure gateway control and industrial gateway > control. I don't dare to apply it without testing. So... can we get qemu-riscv and this board tested for 6.1 (and probably 6.8)? I'll also ask anyone for comments here. The series looked good to me the last time (I may take second look), but I'm likely to apply it if it gets tested and if there are no other comments. Best regards, Pavel
Hello Pavel, > From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On > Behalf Of Pavel Machek via lists.cip-project.org > Sent: Tuesday, January 9, 2024 7:51 PM > > Hi! > > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > Single) > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces > such > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as > > entry-class social infrastructure gateway control and industrial gateway > > control. > > I don't dare to apply it without testing. So... can we get qemu-riscv > and this board tested for 6.1 (and probably 6.8)? Currently we're building using CIP's risc-v qemu config. We'll get test support sorted soon once we have a suitable rootfs. I've done the initial work to build for RZ/Five, see pipeline [0], job [1]. This is using a Renesas specific defconfig [2] that I've created a MR [3] for. [0] https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1135494600 [1] https://gitlab.com/cip-project/cip-kernel/linux-cip/-/jobs/5914246689 [2] https://gitlab.com/patersonc/cip-kernel-config/-/blob/patersonc/add-rzfive-config/6.1.y-cip/riscv/renesas_rzfive_defconfig [3] https://gitlab.com/cip-project/cip-kernel/cip-kernel-config/-/merge_requests/87 I've also done the preparation for boot testing RZ/Five, however before we can use it I need to put an RZ/Five board into the CIP LAVA infrastructure. I've got a board on order for this, so hopefully we can get this sorted next week. I'll keep you updated. Kind regards, Chris > > I'll also ask anyone for comments here. The series looked good to me > the last time (I may take second look), but I'm likely to apply it if > it gets tested and if there are no other comments. > > Best regards, > Pavel > -- > DENX Software Engineering GmbH, Managing Director: Erika Unter > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Hello Pavel, all, > From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On > Behalf Of Chris Paterson via lists.cip-project.org > Sent: Thursday, January 11, 2024 9:16 PM > > Hello Pavel, > > > From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On > > Behalf Of Pavel Machek via lists.cip-project.org > > Sent: Tuesday, January 9, 2024 7:51 PM > > > > Hi! > > > > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > > Single) > > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces > > such > > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as > > > entry-class social infrastructure gateway control and industrial gateway > > > control. > > > > I don't dare to apply it without testing. So... can we get qemu-riscv > > and this board tested for 6.1 (and probably 6.8)? > > Currently we're building using CIP's risc-v qemu config. > We'll get test support sorted soon once we have a suitable rootfs. > > I've done the initial work to build for RZ/Five, see pipeline [0], job [1]. > This is using a Renesas specific defconfig [2] that I've created a MR [3] for. > > [0] > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitla > b.com%2Fcip-project%2Fcip-kernel%2Flinux-cip%2F- > %2Fpipelines%2F1135494600&data=05%7C02%7Cchris.paterson2%40ren > esas.com%7C02bb7316971e4deb9f8f08dc12ea7a30%7C53d82571da1947 > e49cb4625a166a4a2a%7C0%7C0%7C638406045475126479%7CUnknown > %7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1ha > WwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=J%2B4VRFeq8aHpn > Vk%2FEjuoxohV3i0iCJfM3g%2FeAfBAyb0%3D&reserved=0 > [1] > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitla > b.com%2Fcip-project%2Fcip-kernel%2Flinux-cip%2F- > %2Fjobs%2F5914246689&data=05%7C02%7Cchris.paterson2%40renesas > .com%7C02bb7316971e4deb9f8f08dc12ea7a30%7C53d82571da1947e49c > b4625a166a4a2a%7C0%7C0%7C638406045475282677%7CUnknown%7C > TWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiL > CJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=054E9QFWV2Pumxcnma > wxs1yC9vIAsy4qPnhOVRlQtMY%3D&reserved=0 > [2] > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitla > b.com%2Fpatersonc%2Fcip-kernel-config%2F- > %2Fblob%2Fpatersonc%2Fadd-rzfive-config%2F6.1.y- > cip%2Friscv%2Frenesas_rzfive_defconfig&data=05%7C02%7Cchris.paters > on2%40renesas.com%7C02bb7316971e4deb9f8f08dc12ea7a30%7C53d82 > 571da1947e49cb4625a166a4a2a%7C0%7C0%7C638406045475282677% > 7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiL > CJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=9zClQ4l > VfTydYp5b%2BPzYz7bRIil1F56k89R1oig2UUY%3D&reserved=0 > [3] > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitla > b.com%2Fcip-project%2Fcip-kernel%2Fcip-kernel-config%2F- > %2Fmerge_requests%2F87&data=05%7C02%7Cchris.paterson2%40renes > as.com%7C02bb7316971e4deb9f8f08dc12ea7a30%7C53d82571da1947e4 > 9cb4625a166a4a2a%7C0%7C0%7C638406045475282677%7CUnknown% > 7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW > wiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=ba0YxWoRnm%2BkEa > aLbBivPaou8gJkK1k8gEzz0uiDydU%3D&reserved=0 > > I've also done the preparation for boot testing RZ/Five, however before we > can use it I need to put an RZ/Five board > into the CIP LAVA infrastructure. I've got a board on order for this, so > hopefully we can get this sorted next week. > I'll keep you updated. I've now added an RZ/Five platform to lab-cip-renesas so we can test. Tested with a simple boot test based on CIP 6.1 + this patch series: https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1142975670 Please let me know if there is anything else you need. I'll integrate test support into our "official" pipeline once the kernel config MR is merged. https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1142975670 Kind regards, Chris
Hi! > > Currently we're building using CIP's risc-v qemu config. > > We'll get test support sorted soon once we have a suitable rootfs. > > > > I've done the initial work to build for RZ/Five, see pipeline [0], job [1]. > > This is using a Renesas specific defconfig [2] that I've created a MR [3] for. > > > > [0] > > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitla > > b.com%2Fcip-project%2Fcip-kernel%2Flinux-cip%2F- > > %2Fpipelines%2F1135494600&data=05%7C02%7Cchris.paterson2%40ren > > esas.com%7C02bb7316971e4deb9f8f08dc12ea7a30%7C53d82571da1947 > > e49cb4625a166a4a2a%7C0%7C0%7C638406045475126479%7CUnknown > > %7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1ha > > WwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=J%2B4VRFeq8aHpn > > Vk%2FEjuoxohV3i0iCJfM3g%2FeAfBAyb0%3D&reserved=0 Okay, not sure who damaged the link, but I'm not clicking these. > > I've also done the preparation for boot testing RZ/Five, however before we > > can use it I need to put an RZ/Five board > > into the CIP LAVA infrastructure. I've got a board on order for this, so > > hopefully we can get this sorted next week. > > I'll keep you updated. > > I've now added an RZ/Five platform to lab-cip-renesas so we can test. > Tested with a simple boot test based on CIP 6.1 + this patch series: > https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1142975670 Ok, green tick, that's good I think. > Please let me know if there is anything else you need. > > I'll integrate test support into our "official" pipeline once the kernel config MR is merged. > https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1142975670 Thanks for testing. It looks like I'll simply push the RFC I had in my tree. Geronimo! Pavel
Hi All, The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as entry-class social infrastructure gateway control and industrial gateway control. This patch series adds initial SoC DTSi support for Renesas RZ/Five (R9A07G043) SoC and updates the bindings for the same. Below is the list of IP blocks which will be supported by this series: - ADC - AX45MP CPU - CANFD - CPG - DMAC - Ethernet - I2C - OSTM - PINCTRL - PLIC - RSPI - SCIF - SDHI/eMMC - SSIF - SYSC - Thermal - USB Host/Device - WDT Apart from first two patches all the patches have been cherry picked from upstream kernel. As discussed in CIP IRC meeting I am sending the v1 series, no code changes have been done as compared to RFC series. RFC -> v1: * Rebased the changes on top of 6.1.y-cip RFC series: * https://patchwork.kernel.org/project/cip-dev/cover/20231220230646.219816-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Cheers, Prabhakar Arnd Bergmann (2): riscv: dma-mapping: only invalidate after DMA, not flush riscv: dma-mapping: skip invalidation before bidirectional DMA Conor Dooley (1): riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node Jisheng Zhang (1): riscv: mm: mark noncoherent_supported as __ro_after_init Lad Prabhakar (25): arm64: dts: renesas: rzg2ul-smarc: Drop including RZ/G2UL SoM DTSI arm64: dts: renesas: rzg2ul: Move PMOD_SCI0_EN macro to board DTS mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option dependant on ARCH_RENESAS clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback riscv: Kconfig: Enable cpufreq kconfig menu dt-bindings: riscv: Sort the CPU core list alphabetically dt-bindings: riscv: Add Andes AX45MP core to the list riscv: dma-mapping: switch over to generic implementation riscv: asm: vendorid_list: Add Andes Technology to the vendors list riscv: errata: Add Andes alternative ports riscv: mm: dma-noncoherent: nonstandard cache operations support dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller cache: Add L2 cache management for Andes AX45MP RISC-V core soc: renesas: Kconfig: Select the required configs for RZ/Five SoC riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C riscv: dts: renesas: rzfive-smarc-som: Enable WDT riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1} riscv: dts: renesas: r9a07g043f: Add L2 cache node riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled Samuel Holland (1): clocksource/drivers/riscv: Increase the clock source rating .../cache/andestech,ax45mp-cache.yaml | 81 +++++++ .../devicetree/bindings/riscv/cpus.yaml | 11 +- MAINTAINERS | 7 + .../boot/dts/renesas/r9a07g043u11-smarc.dts | 3 + arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 4 - arch/riscv/Kconfig | 10 +- arch/riscv/Kconfig.erratas | 21 ++ arch/riscv/Kconfig.socs | 5 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/renesas/Makefile | 2 + arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 72 ++++++ .../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 +++ .../boot/dts/renesas/rzfive-smarc-som.dtsi | 24 ++ arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 8 + arch/riscv/errata/Makefile | 1 + arch/riscv/errata/andes/Makefile | 1 + arch/riscv/errata/andes/errata.c | 66 ++++++ arch/riscv/include/asm/alternative.h | 3 + arch/riscv/include/asm/dma-noncoherent.h | 28 +++ arch/riscv/include/asm/errata_list.h | 5 + arch/riscv/include/asm/vendorid_list.h | 1 + arch/riscv/kernel/alternative.c | 5 + arch/riscv/kernel/time.c | 9 - arch/riscv/mm/dma-noncoherent.c | 105 ++++++++- drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/cache/Kconfig | 11 + drivers/cache/Makefile | 3 + drivers/cache/ax45mp_cache.c | 213 ++++++++++++++++++ drivers/clocksource/timer-riscv.c | 7 +- drivers/mmc/host/Kconfig | 4 +- drivers/soc/renesas/Kconfig | 4 + 32 files changed, 713 insertions(+), 32 deletions(-) create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml create mode 100644 arch/riscv/boot/dts/renesas/Makefile create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi create mode 100644 arch/riscv/errata/andes/Makefile create mode 100644 arch/riscv/errata/andes/errata.c create mode 100644 arch/riscv/include/asm/dma-noncoherent.h create mode 100644 drivers/cache/Kconfig create mode 100644 drivers/cache/Makefile create mode 100644 drivers/cache/ax45mp_cache.c