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[5.10.y-cip,0/6] Versa3 clk driver improvements

Message ID 20240202122338.309435-1-biju.das.jz@bp.renesas.com (mailing list archive)
Headers show
Series Versa3 clk driver improvements | expand

Message

Biju Das Feb. 2, 2024, 12:23 p.m. UTC
This patch series aims to improve versa3 clock driver.

All the patches are cherry-picked from the mainline.

Biju Das (6):
  arm64: defconfig: Enable Renesas VersaClock 3 clock generator config
  clk: versaclock3: Update vc3_get_div() to avoid divide by zero
  clk: versaclock3: Avoid unnecessary padding
  clk: versaclock3: Use u8 return type for get_parent() callback
  clk: versaclock3: Add missing space between ')' and '{'
  clk: versaclock3: Drop ret variable

 arch/arm64/configs/defconfig  |  1 +
 drivers/clk/clk-versaclock3.c | 88 ++++++++++++++++-------------------
 2 files changed, 41 insertions(+), 48 deletions(-)

Comments

Pavel Machek Feb. 5, 2024, 6:22 p.m. UTC | #1
Hi!

> This patch series aims to improve versa3 clock driver.
> 
> All the patches are cherry-picked from the mainline.

Series looks ok to me, I can apply it if it passes testing and if
there are no other comments.

Best regards,
								Pavel
Pavel Machek Feb. 6, 2024, 10:50 a.m. UTC | #2
Hi!

> This patch series aims to improve versa3 clock driver.
> 
> All the patches are cherry-picked from the mainline.
> 
> Biju Das (6):
>   arm64: defconfig: Enable Renesas VersaClock 3 clock generator config
>   clk: versaclock3: Update vc3_get_div() to avoid divide by zero
>   clk: versaclock3: Avoid unnecessary padding
>   clk: versaclock3: Use u8 return type for get_parent() callback
>   clk: versaclock3: Add missing space between ')' and '{'
>   clk: versaclock3: Drop ret variable

Thank you, applied.

Best regards,
								Pavel