Message ID | 20240202122338.309435-1-biju.das.jz@bp.renesas.com (mailing list archive) |
---|---|
Headers | show |
Series | Versa3 clk driver improvements | expand |
Hi! > This patch series aims to improve versa3 clock driver. > > All the patches are cherry-picked from the mainline. Series looks ok to me, I can apply it if it passes testing and if there are no other comments. Best regards, Pavel
Hi! > This patch series aims to improve versa3 clock driver. > > All the patches are cherry-picked from the mainline. > > Biju Das (6): > arm64: defconfig: Enable Renesas VersaClock 3 clock generator config > clk: versaclock3: Update vc3_get_div() to avoid divide by zero > clk: versaclock3: Avoid unnecessary padding > clk: versaclock3: Use u8 return type for get_parent() callback > clk: versaclock3: Add missing space between ')' and '{' > clk: versaclock3: Drop ret variable Thank you, applied. Best regards, Pavel