| Message ID | 20250321110021.3612805-1-tommaso.merciai.xr@bp.renesas.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add support for Renesas RZ/G3E SoC and SMARC-EVK platform | expand |
Hi! > This patch series adds initial support for the Renesas RZ/G3E SoC and > RZ/G3E SMARC EVK platform to linux-6.1.y-cip kernel. The RZ/G3E device is a > general-purpose microprocessor with a quad-core CA-55, single core CM-33, > Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals. > > All patches are cherry-picked from mainline kernel. Ok, thanks for the series, it looks good to me. Should I simply try to apply it to both 6.1 and 6.12? I guess I can do that if there are no other comments. Best regards, Pavel
Hi Pavel, Thanks for your comment. On Fri, Mar 21, 2025 at 09:12:28PM +0100, Pavel Machek wrote: > Hi! > > > This patch series adds initial support for the Renesas RZ/G3E SoC and > > RZ/G3E SMARC EVK platform to linux-6.1.y-cip kernel. The RZ/G3E device is a > > general-purpose microprocessor with a quad-core CA-55, single core CM-33, > > Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals. > > > > All patches are cherry-picked from mainline kernel. > > Ok, thanks for the series, it looks good to me. > > Should I simply try to apply it to both 6.1 and 6.12? I guess I can do > that if there are no other comments. I tested on my side and I can share that the following patches are needed to boot the board on top of be95b49207284 (linux-6.12.y-cip): abf61442f5523 (HEAD) arm64: defconfig: Enable R9A09G047 SoC 5fe2ef2536b4b soc: renesas: Add RZ/G3E (R9A09G047) config option 0b2bbca0cccdc arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board b39f424adff45 arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM b1f6a3f53e512 arm64: dts: renesas: r9a09g047: Add OPP table a89ab4d1d72ad arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC 0545748b50260 clk: renesas: r9a09g047: Add CA55 core clocks 53902b5dba919 clk: renesas: rzv2h: Add support for RZ/G3E SoC a1721e1ab4092 clk: renesas: rzv2h: Add MSTOP support c5e58c15e5b02 clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets 6e9acef8a72fd clk: renesas: r9a09g057: Add clock and reset entries for ICU 13f8ef8afecea clk: renesas: r9a09g057: Add CA55 core clocks f53d5c3439ebf clk: renesas: rzv2h: Add selective Runtime PM support for clocks 510f8e3823b22 dt-bindings: clock: renesas: Document RZ/G3E SoC CPG bcb927d43ed05 dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK 541305514cdf5 dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants Patches need some really small rework, (just moving up/down things to be applied). Test log: root@smarc-rzg3e:~# uname -r 6.12.19-00045-gabf61442f552 root@smarc-rzg3e:~# cat /proc/cpuinfo processor : 0 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 processor : 1 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 processor : 2 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 processor : 3 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 root@smarc-rzg3e:~# cat /proc/meminfo MemTotal: 3883788 kB MemFree: 3569016 kB MemAvailable: 3503672 kB root@smarc-rzg3e:~# cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 11: 5442 5213 7158 10565 GICv3 27 Level arch_timer 14: 0 0 0 0 GICv3 561 Level 11c01400.serial:rx err 15: 1 0 0 0 GICv3 564 Level 11c01400.serial:rx full 16: 1668 0 0 0 GICv3 565 Level 11c01400.serial:tx empty 17: 0 0 0 0 GICv3 562 Level 11c01400.serial:break 18: 116 0 0 0 GICv3 566 Level 11c01400.serial:rx ready 19: 0 0 0 0 GICv3 563 Level 11c01400.serial:tx end IPI0: 403 479 131 286 Rescheduling interrupts IPI1: 4293 4511 1482 4291 Function call interrupts IPI2: 0 0 0 0 CPU stop interrupts IPI3: 0 0 0 0 CPU stop NMIs IPI4: 0 0 0 0 Timer broadcast interrupts IPI5: 447 524 272 565 IRQ work interrupts IPI6: 0 0 0 0 CPU backtrace interrupts IPI7: 0 0 0 0 KGDB roundup interrupts Err: 0 > > Best regards, > Pavel > -- > DENX Software Engineering GmbH, Managing Director: Erika Unter > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Thanks & Regards, Tommaso
Hi! > > > This patch series adds initial support for the Renesas RZ/G3E SoC and > > > RZ/G3E SMARC EVK platform to linux-6.1.y-cip kernel. The RZ/G3E device is a > > > general-purpose microprocessor with a quad-core CA-55, single core CM-33, > > > Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals. > > > > > > All patches are cherry-picked from mainline kernel. > > > > Ok, thanks for the series, it looks good to me. > > > > Should I simply try to apply it to both 6.1 and 6.12? I guess I can do > > that if there are no other comments. > > I tested on my side and I can share that the following patches are needed > to boot the board on top of be95b49207284 (linux-6.12.y-cip): > > abf61442f5523 (HEAD) arm64: defconfig: Enable R9A09G047 SoC > 5fe2ef2536b4b soc: renesas: Add RZ/G3E (R9A09G047) config option > 0b2bbca0cccdc arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board > b39f424adff45 arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM > b1f6a3f53e512 arm64: dts: renesas: r9a09g047: Add OPP table > a89ab4d1d72ad arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC > 0545748b50260 clk: renesas: r9a09g047: Add CA55 core clocks > 53902b5dba919 clk: renesas: rzv2h: Add support for RZ/G3E SoC > a1721e1ab4092 clk: renesas: rzv2h: Add MSTOP support > c5e58c15e5b02 clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets > 6e9acef8a72fd clk: renesas: r9a09g057: Add clock and reset entries for ICU > 13f8ef8afecea clk: renesas: r9a09g057: Add CA55 core clocks > f53d5c3439ebf clk: renesas: rzv2h: Add selective Runtime PM support for clocks > 510f8e3823b22 dt-bindings: clock: renesas: Document RZ/G3E SoC CPG > bcb927d43ed05 dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK > 541305514cdf5 dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants > > Patches need some really small rework, (just moving up/down things to be > applied). Can you submit them as a series, please? Best regards, Pavel
Hi! > This patch series adds initial support for the Renesas RZ/G3E SoC and > RZ/G3E SMARC EVK platform to linux-6.1.y-cip kernel. The RZ/G3E device is a > general-purpose microprocessor with a quad-core CA-55, single core CM-33, > Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals. > > All patches are cherry-picked from mainline kernel. Thank you, applied. Best regards, Pavel
Hi Pavel, On Wed, Mar 26, 2025 at 01:54:41PM +0100, Pavel Machek wrote: > Hi! > > > This patch series adds initial support for the Renesas RZ/G3E SoC and > > RZ/G3E SMARC EVK platform to linux-6.1.y-cip kernel. The RZ/G3E device is a > > general-purpose microprocessor with a quad-core CA-55, single core CM-33, > > Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals. > > > > All patches are cherry-picked from mainline kernel. > > Thank you, applied. Thanks for the update! :) Next step will be: pinctrl support This for 6.1.y-cip will be a patchset from: [6.1.y-cip,23/85] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H .. to [6.1.y-cip,64/85] arm64: dts: renesas: r9a09g047: Add pincontrol node + [6.1.y-cip,77/85] arm64: dts: renesas: r9a09g047e57-smarc: Add SCIF pincontrol What do you think? Thanks in advance. ---- I've tested the same on 6.12.y-cip. I can share that a smaller patchset is required to bring up the pinctrl support + SCIF pincontrol on RZ/G3E. 21eaffd338902 arm64: dts: renesas: r9a09g047e57-smarc: Add SCIF pincontrol 60e58e522d319 arm64: dts: renesas: r9a09g047: Add pincontrol node e3acc80c6ba8f pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC 92421d6d2daf2 pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg table ad84e8733dfb2 pinctrl: renesas: rzg2l: Use gpiochip_populate_parent_fwspec_twocell helper 729b42260235e pinctrl: renesas: rzg2l: Add support for configuring schmitt-trigger ec01f77780384 pinctrl: renesas: rzg2l: Add support for enabling/disabling open-drain outputs d29a0e1f3a42f pinctrl: renesas: rzg2l: Remove RZG2L_TINT_IRQ_START_INDEX 64772cc20274c pinctrl: renesas: rzg2l: Move RZG2L_SINGLE_PIN definition to top of the file da0cd8ac391d8 dt-bindings: pinctrl: renesas: Document RZ/G3E SoC 4cbfebe8e22d1 dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow schmitt and open drain properties 63f78eb380bd8 dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoC 35cfeaff9607d dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H I will send the series. > > Best regards, > Pavel > -- > DENX Software Engineering GmbH, Managing Director: Erika Unter > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Thanks & Regards, Tommmaso
Hi! > > > This patch series adds initial support for the Renesas RZ/G3E SoC and > > > RZ/G3E SMARC EVK platform to linux-6.1.y-cip kernel. The RZ/G3E device is a > > > general-purpose microprocessor with a quad-core CA-55, single core CM-33, > > > Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals. > > > > > > All patches are cherry-picked from mainline kernel. > > > > Thank you, applied. > > Thanks for the update! :) > > Next step will be: pinctrl support > > This for 6.1.y-cip will be a patchset from: > > [6.1.y-cip,23/85] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H > .. > to > [6.1.y-cip,64/85] arm64: dts: renesas: r9a09g047: Add pincontrol node > + > [6.1.y-cip,77/85] arm64: dts: renesas: r9a09g047e57-smarc: Add SCIF pincontrol Series of 40 patches is still a bit big, but if you can't split them more... just submit, we'll likely deal with them eventually. Both 6.1 and 6.12 versions, please. Best regards, Pavel
Hi Pavel, On Mon, Mar 31, 2025 at 11:07:10AM +0200, Pavel Machek wrote: > Hi! > > > > > This patch series adds initial support for the Renesas RZ/G3E SoC and > > > > RZ/G3E SMARC EVK platform to linux-6.1.y-cip kernel. The RZ/G3E device is a > > > > general-purpose microprocessor with a quad-core CA-55, single core CM-33, > > > > Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals. > > > > > > > > All patches are cherry-picked from mainline kernel. > > > > > > Thank you, applied. > > > > Thanks for the update! :) > > > > Next step will be: pinctrl support > > > > This for 6.1.y-cip will be a patchset from: > > > > [6.1.y-cip,23/85] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H > > .. > > to > > [6.1.y-cip,64/85] arm64: dts: renesas: r9a09g047: Add pincontrol node > > + > > [6.1.y-cip,77/85] arm64: dts: renesas: r9a09g047e57-smarc: Add SCIF pincontrol > > Series of 40 patches is still a bit big, but if you can't split them > more... just submit, we'll likely deal with them eventually. Both 6.1 > and 6.12 versions, please. Will do. Thanks for your feedback. > > Best regards, > Pavel > -- > DENX Software Engineering GmbH, Managing Director: Erika Unter > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Regards, Tommaso
Dear All, This patch series adds initial support for the Renesas RZ/G3E SoC and RZ/G3E SMARC EVK platform to linux-6.1.y-cip kernel. The RZ/G3E device is a general-purpose microprocessor with a quad-core CA-55, single core CM-33, Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals. All patches are cherry-picked from mainline kernel. base commit: - d08cad4e6b10: serial: sh-sci: Increment the runtime usage counter for the earlycon device Test logs: # uname -r 6.1.129-cip38-00033-gb59158b647b6 root@smarc-rzg3e:~# cat /proc/cpuinfo processor : 0 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 processor : 1 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 processor : 2 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 processor : 3 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 root@smarc-rzg3e:~# cat /proc/meminfo MemTotal: 3888744 kB MemFree: 3585072 kB MemAvailable: 3519384 kB root@smarc-rzg3e:~# cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 11: 2884 2689 2611 2768 GICv3 27 Level arch_timer 14: 0 0 0 0 GICv3 561 Level 11c01400.serial:rx err 15: 1 0 0 0 GICv3 564 Level 11c01400.serial:rx full 16: 1241 0 0 0 GICv3 565 Level 11c01400.serial:tx empty 17: 0 0 0 0 GICv3 562 Level 11c01400.serial:break 18: 49 0 0 0 GICv3 566 Level 11c01400.serial:rx ready 19: 0 0 0 0 GICv3 563 Level 11c01400.serial:tx end IPI0: 261 139 301 201 Rescheduling interrupts IPI1: 2768 2155 2133 1553 Function call interrupts IPI2: 0 0 0 0 CPU stop interrupts IPI3: 0 0 0 0 CPU stop (for crash dump) interrupts IPI4: 0 0 0 0 Timer broadcast interrupts IPI5: 186 156 150 171 IRQ work interrupts IPI6: 0 0 0 0 CPU wake-up interrupts Err: 0 Thanks & Regards, Tommaso Biju Das (12): dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK dt-bindings: clock: renesas: Document RZ/G3E SoC CPG clk: renesas: rzv2h: Add MSTOP support clk: renesas: rzv2h: Add support for RZ/G3E SoC clk: renesas: r9a09g047: Add CA55 core clocks arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC arm64: dts: renesas: r9a09g047: Add OPP table arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board soc: renesas: Add RZ/G3E (R9A09G047) config option arm64: defconfig: Enable R9A09G047 SoC Fabrizio Castro (1): clk: renesas: r9a09g057: Add clock and reset entries for ICU Lad Prabhakar (8): dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG clk: renesas: Add family-specific clock driver for RZ/V2H(P) clk: renesas: Add RZ/V2H(P) CPG driver clk: renesas: rzv2h: Add support for dynamic switching divider clocks clk: renesas: rzv2h: Add selective Runtime PM support for clocks clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT clk: renesas: r9a09g057: Add CA55 core clocks clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets .../devicetree/bindings/arm/renesas.yaml | 17 + .../bindings/clock/renesas,rzv2h-cpg.yaml | 83 ++ arch/arm64/boot/dts/renesas/Makefile | 2 + arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 185 ++++ arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi | 18 + .../boot/dts/renesas/r9a09g047e57-smarc.dts | 18 + arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi | 13 + .../boot/dts/renesas/renesas-smarc2.dtsi | 24 + .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 28 + arch/arm64/configs/defconfig | 1 + drivers/clk/renesas/Kconfig | 14 + drivers/clk/renesas/Makefile | 3 + drivers/clk/renesas/r9a09g047-cpg.c | 118 +++ drivers/clk/renesas/r9a09g057-cpg.c | 280 +++++ drivers/clk/renesas/rzv2h-cpg.c | 999 ++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 224 ++++ drivers/soc/renesas/Kconfig | 5 + .../dt-bindings/clock/renesas,r9a09g047-cpg.h | 21 + .../dt-bindings/clock/renesas,r9a09g057-cpg.h | 21 + 19 files changed, 2074 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi create mode 100644 arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi create mode 100644 arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi create mode 100644 drivers/clk/renesas/r9a09g047-cpg.c create mode 100644 drivers/clk/renesas/r9a09g057-cpg.c create mode 100644 drivers/clk/renesas/rzv2h-cpg.c create mode 100644 drivers/clk/renesas/rzv2h-cpg.h create mode 100644 include/dt-bindings/clock/renesas,r9a09g047-cpg.h create mode 100644 include/dt-bindings/clock/renesas,r9a09g057-cpg.h