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Fri, 21 Mar 2025 11:00:42 +0000 From: Tommaso Merciai To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek CC: Biju Das , Lad Prabhakar , tomm.merciai@gmail.com Subject: [PATCH 6.1.y-cip 00/21] Add support for Renesas RZ/G3E SoC and SMARC-EVK platform Date: Fri, 21 Mar 2025 12:00:00 +0100 Message-ID: <20250321110021.3612805-1-tommaso.merciai.xr@bp.renesas.com> X-Mailer: git-send-email 2.43.0 X-ClientProxiedBy: FR4P281CA0077.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:cd::17) To OS9PR01MB13950.jpnprd01.prod.outlook.com (2603:1096:604:35e::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OS9PR01MB13950:EE_|OS9PR01MB12437:EE_ X-MS-Office365-Filtering-Correlation-Id: 97e3d5b0-d05c-4058-4ec3-08dd68679f29 X-LD-Processed: 53d82571-da19-47e4-9cb4-625a166a4a2a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014|52116014|38350700014; X-Microsoft-Antispam-Message-Info: f1QCwzezEcCObuN+LEKQvIQNz/6CUghbz83ytrc53ESUuLig5QYgS9rtnfBTPHFl42aNu7pqfBmDDMukxGN2XzzrXYg3fYWZ9gI5Q94Gmx/kvg2i8wYJpayD8aiW8NpXt55rtxhVdNFj9yKT/IkeCGWfttboi2hil1UeJl+BYKpk7DwavRP4sl0SDyqGPW7GEu8vJenZRuIvXoNtGF63vM+ThSCP7iAW1oRCnulsn7kQm3ELCqyyKhvcC0rz92qQnYgH7jjaY7Hr5XCENI65gqM2Gx47a0sm4laQkH75B3iSU/Omtnbsrd0F+QlvdZJY+sDBDfmN1/qW92h5KWmkqatBMcXS7Hjli7hSnru62ruyAh/9d9YzRFxia9L9izongrik+b2VE5htQvn0eAb2hMQlR/0n36pVYXgRQLp3IJPWQbpK6D54+lE5EbFWN7C7j+MQBaRDgonww0Jrnc0DMiq+hFbUB62yYPHx3dc6j4hgvU48RyfLV4CjECeiVj6SEmpzxb/FSK5uIj2RiY3tg5tlnpwYaehCG4eLnzc/XOG48ecVUDvQZPypwHoXzd6KPzJA0xyq9pwERY4iVqjSON+17gOSAYs5uoDiAyriuKhVyi5WQQRxz6g2eRegtUbhFDlTtr1TTKeL0CCae3Rof/ZGZGN8118qru9Frd5ZOs2BUvaG+EtrHekzhyXOOhX0TN5+JSybo7UzMQlmCOl74B+EM8JfHnMpmR+7ZMtxG+sYZNKRMucvh/xj45TlMuP0W6XFm+1wSArgl8rQXm2tKKlPqGeY5fGtDQ0iN9EXUeUWPup8OJG7nL6IQX2wx5uWEfz7di86bHHD8pTDKOoj0TUnFoEJS6Oc69bTT30tJDVOk26XM3WIxPj7hvy7pCFTHWNnC2fB+gvZbMg8S54yjs5vydIpaEJbGcBOBYUKuVZeqiBG+sjTI0h6lxq571GcsSVz3VF4m5hgGLP013N/OPn6/Y6ack2KJsim/1Ox5LtNshskdr1Cgp8aYdfpnbvfUAIwE3V9MV1KxSXsErraS5X7ecFsU56pHXAaoiO9zYa9PVaRy6Hb8QvDmb4wByq9x2ILj5p09ZV0A9jnAsYf5QEi/GOITiGAHu3xM3e7+nEgvk+BOYx6HBBA0jgIaX6pE+IzjhaHAgJK+yXtWkP1RmqT7X8yC+JfOu57ZzZOvlzlb/oTRpCe1q/dtogngYTY3oPRYS1iga/oLWFijvW+ZQJfVzib3TkMqMhbS9waYgUnzhLgC6w5Immkl+9BSZwRT3d39+8cRUIlo+6/DmNi8vxWeWer3SyrrkqXONSMYkP4rN7vGmLj7kOAJ7LhLMZMrufS+qAhX7AWskRuu2zV0dHqkBcNWbfoyJQZBbsHAYWknkJ8hu/RQ51CeCfrkf1zXZ1TxTGnns+diMU7wxX8odi+WQZwyIEmqAuw+Ovb36te7LEKgEtek6lyROh8bhp0 X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:OS9PR01MB13950.jpnprd01.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(1800799024)(376014)(52116014)(38350700014);DIR:OUT;SFP:1101; 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Fri, 21 Mar 2025 11:00:59 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/18307 Dear All, This patch series adds initial support for the Renesas RZ/G3E SoC and RZ/G3E SMARC EVK platform to linux-6.1.y-cip kernel. The RZ/G3E device is a general-purpose microprocessor with a quad-core CA-55, single core CM-33, Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals. All patches are cherry-picked from mainline kernel. base commit: - d08cad4e6b10: serial: sh-sci: Increment the runtime usage counter for the earlycon device Test logs: # uname -r 6.1.129-cip38-00033-gb59158b647b6 root@smarc-rzg3e:~# cat /proc/cpuinfo processor : 0 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 processor : 1 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 processor : 2 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 processor : 3 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 root@smarc-rzg3e:~# cat /proc/meminfo MemTotal: 3888744 kB MemFree: 3585072 kB MemAvailable: 3519384 kB root@smarc-rzg3e:~# cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 11: 2884 2689 2611 2768 GICv3 27 Level arch_timer 14: 0 0 0 0 GICv3 561 Level 11c01400.serial:rx err 15: 1 0 0 0 GICv3 564 Level 11c01400.serial:rx full 16: 1241 0 0 0 GICv3 565 Level 11c01400.serial:tx empty 17: 0 0 0 0 GICv3 562 Level 11c01400.serial:break 18: 49 0 0 0 GICv3 566 Level 11c01400.serial:rx ready 19: 0 0 0 0 GICv3 563 Level 11c01400.serial:tx end IPI0: 261 139 301 201 Rescheduling interrupts IPI1: 2768 2155 2133 1553 Function call interrupts IPI2: 0 0 0 0 CPU stop interrupts IPI3: 0 0 0 0 CPU stop (for crash dump) interrupts IPI4: 0 0 0 0 Timer broadcast interrupts IPI5: 186 156 150 171 IRQ work interrupts IPI6: 0 0 0 0 CPU wake-up interrupts Err: 0 Thanks & Regards, Tommaso Biju Das (12): dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK dt-bindings: clock: renesas: Document RZ/G3E SoC CPG clk: renesas: rzv2h: Add MSTOP support clk: renesas: rzv2h: Add support for RZ/G3E SoC clk: renesas: r9a09g047: Add CA55 core clocks arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC arm64: dts: renesas: r9a09g047: Add OPP table arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board soc: renesas: Add RZ/G3E (R9A09G047) config option arm64: defconfig: Enable R9A09G047 SoC Fabrizio Castro (1): clk: renesas: r9a09g057: Add clock and reset entries for ICU Lad Prabhakar (8): dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG clk: renesas: Add family-specific clock driver for RZ/V2H(P) clk: renesas: Add RZ/V2H(P) CPG driver clk: renesas: rzv2h: Add support for dynamic switching divider clocks clk: renesas: rzv2h: Add selective Runtime PM support for clocks clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT clk: renesas: r9a09g057: Add CA55 core clocks clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets .../devicetree/bindings/arm/renesas.yaml | 17 + .../bindings/clock/renesas,rzv2h-cpg.yaml | 83 ++ arch/arm64/boot/dts/renesas/Makefile | 2 + arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 185 ++++ arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi | 18 + .../boot/dts/renesas/r9a09g047e57-smarc.dts | 18 + arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi | 13 + .../boot/dts/renesas/renesas-smarc2.dtsi | 24 + .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 28 + arch/arm64/configs/defconfig | 1 + drivers/clk/renesas/Kconfig | 14 + drivers/clk/renesas/Makefile | 3 + drivers/clk/renesas/r9a09g047-cpg.c | 118 +++ drivers/clk/renesas/r9a09g057-cpg.c | 280 +++++ drivers/clk/renesas/rzv2h-cpg.c | 999 ++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 224 ++++ drivers/soc/renesas/Kconfig | 5 + .../dt-bindings/clock/renesas,r9a09g047-cpg.h | 21 + .../dt-bindings/clock/renesas,r9a09g057-cpg.h | 21 + 19 files changed, 2074 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi create mode 100644 arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi create mode 100644 arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi create mode 100644 drivers/clk/renesas/r9a09g047-cpg.c create mode 100644 drivers/clk/renesas/r9a09g057-cpg.c create mode 100644 drivers/clk/renesas/rzv2h-cpg.c create mode 100644 drivers/clk/renesas/rzv2h-cpg.h create mode 100644 include/dt-bindings/clock/renesas,r9a09g047-cpg.h create mode 100644 include/dt-bindings/clock/renesas,r9a09g057-cpg.h