| Message ID | 20250325145611.3595454-1-tommaso.merciai.xr@bp.renesas.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add support for Renesas RZ/G3E SoC and SMARC-EVK platform | expand |
Hi! > This patch series adds initial support for the Renesas RZ/G3E SoC and > RZ/G3E SMARC EVK platform to linux-6.12.y-cip kernel. The RZ/G3E device is a > general-purpose microprocessor with a quad-core CA-55, single core CM-33, > Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals. Thank you. It looks good on quick scan, I'll apply it if it passes testing and there are no other comments. Best regards, Pavel
Hi Pavel, > -----Original Message----- > From: Pavel Machek <pavel@denx.de> > Sent: Tuesday, March 25, 2025 9:14 PM > To: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> > Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu > <nobuhiro1.iwamatsu@toshiba.co.jp>; Biju Das <biju.das.jz@bp.renesas.com>; > Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; Tommaso > Merciai <tomm.merciai@gmail.com> > Subject: Re: [PATCH 6.12.y-cip 00/16] Add support for Renesas RZ/G3E SoC > and SMARC-EVK platform > > Hi! > > > This patch series adds initial support for the Renesas RZ/G3E SoC and > > RZ/G3E SMARC EVK platform to linux-6.12.y-cip kernel. The RZ/G3E > > device is a general-purpose microprocessor with a quad-core CA-55, > > single core CM-33, > > Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals. > > Thank you. It looks good on quick scan, I'll apply it if it passes testing > and there are no other comments. Thanks for your work! > > Best regards, > Pavel > -- > DENX Software Engineering GmbH, Managing Director: Erika Unter > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Kind Regards, Tommaso
Hi! > This patch series adds initial support for the Renesas RZ/G3E SoC and > RZ/G3E SMARC EVK platform to linux-6.12.y-cip kernel. The RZ/G3E device is a > general-purpose microprocessor with a quad-core CA-55, single core CM-33, > Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals. > > All patches are cherry-picked from mainline kernel. Thank you, applied. Best regards, Pavel
Dear All, This patch series adds initial support for the Renesas RZ/G3E SoC and RZ/G3E SMARC EVK platform to linux-6.12.y-cip kernel. The RZ/G3E device is a general-purpose microprocessor with a quad-core CA-55, single core CM-33, Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals. All patches are cherry-picked from mainline kernel. base commit: be95b49207284 Add configuration for gitlab-ci. Test logs from linux-6.12.y-cip: root@smarc-rzg3e:~# uname -r 6.12.19-00045-gabf61442f552 root@smarc-rzg3e:~# cat /proc/cpuinfo processor : 0 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 processor : 1 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 processor : 2 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 processor : 3 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 root@smarc-rzg3e:~# cat /proc/meminfo MemTotal: 3883788 kB MemFree: 3565028 kB MemAvailable: 3499708 kB root@smarc-rzg3e:~# cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 11: 2780 2944 2562 2246 GICv3 27 Level arch_timer 14: 0 0 0 0 GICv3 561 Level 11c01400.serial:rx err 15: 1 0 0 0 GICv3 564 Level 11c01400.serial:rx full 16: 1524 0 0 0 GICv3 565 Level 11c01400.serial:tx empty 17: 0 0 0 0 GICv3 562 Level 11c01400.serial:break 18: 73 0 0 0 GICv3 566 Level 11c01400.serial:rx ready 19: 0 0 0 0 GICv3 563 Level 11c01400.serial:tx end IPI0: 225 437 170 261 Rescheduling interrupts IPI1: 2928 3415 1858 3132 Function call interrupts IPI2: 0 0 0 0 CPU stop interrupts IPI3: 0 0 0 0 CPU stop NMIs IPI4: 0 0 0 0 Timer broadcast interrupts IPI5: 278 353 190 188 IRQ work interrupts IPI6: 0 0 0 0 CPU backtrace interrupts IPI7: 0 0 0 0 KGDB roundup interrupts Err: 0 Thanks & Regards, Tommaso Biju Das (12): dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK dt-bindings: clock: renesas: Document RZ/G3E SoC CPG clk: renesas: rzv2h: Add MSTOP support clk: renesas: rzv2h: Add support for RZ/G3E SoC clk: renesas: r9a09g047: Add CA55 core clocks arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC arm64: dts: renesas: r9a09g047: Add OPP table arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board soc: renesas: Add RZ/G3E (R9A09G047) config option arm64: defconfig: Enable R9A09G047 SoC Fabrizio Castro (1): clk: renesas: r9a09g057: Add clock and reset entries for ICU Lad Prabhakar (3): clk: renesas: rzv2h: Add selective Runtime PM support for clocks clk: renesas: r9a09g057: Add CA55 core clocks clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets .../bindings/clock/renesas,rzv2h-cpg.yaml | 15 +- .../bindings/soc/renesas/renesas.yaml | 17 ++ arch/arm64/boot/dts/renesas/Makefile | 2 + arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 185 +++++++++++++++++ arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi | 18 ++ .../boot/dts/renesas/r9a09g047e57-smarc.dts | 18 ++ arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi | 13 ++ .../boot/dts/renesas/renesas-smarc2.dtsi | 24 +++ .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 28 +++ arch/arm64/configs/defconfig | 1 + drivers/clk/renesas/Kconfig | 7 +- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a09g047-cpg.c | 118 +++++++++++ drivers/clk/renesas/r9a09g057-cpg.c | 192 +++++++++++++---- drivers/clk/renesas/rzv2h-cpg.c | 196 +++++++++++++++--- drivers/clk/renesas/rzv2h-cpg.h | 44 +++- drivers/soc/renesas/Kconfig | 5 + .../dt-bindings/clock/renesas,r9a09g047-cpg.h | 21 ++ 18 files changed, 830 insertions(+), 75 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi create mode 100644 arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi create mode 100644 arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi create mode 100644 drivers/clk/renesas/r9a09g047-cpg.c create mode 100644 include/dt-bindings/clock/renesas,r9a09g047-cpg.h