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Tue, 25 Mar 2025 14:56:33 +0000 From: Tommaso Merciai To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek CC: Biju Das , Lad Prabhakar , tomm.merciai@gmail.com Subject: [PATCH 6.12.y-cip 00/16] Add support for Renesas RZ/G3E SoC and SMARC-EVK platform Date: Tue, 25 Mar 2025 15:55:54 +0100 Message-ID: <20250325145611.3595454-1-tommaso.merciai.xr@bp.renesas.com> X-Mailer: git-send-email 2.43.0 X-ClientProxiedBy: FR0P281CA0113.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:a8::13) To OS9PR01MB13950.jpnprd01.prod.outlook.com (2603:1096:604:35e::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OS9PR01MB13950:EE_|TYRPR01MB13248:EE_ X-MS-Office365-Filtering-Correlation-Id: c36f7ec2-e6db-40e0-1c01-08dd6bad3b91 X-LD-Processed: 53d82571-da19-47e4-9cb4-625a166a4a2a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|52116014|376014|1800799024|366016|38350700014; X-Microsoft-Antispam-Message-Info: IW3a1VY7SZoUIvPpoVj2Vv9staoIeA8ED8bTG1MNV5gC9YcRhAS9sIc7f+5GD4ikSQLK8MK4Z8r/nSoVN/LdVmVpzl2j59avBGTTFNOvHL74tX5tnUg7t8Ha6z0FvGa4c7azelH5kxPv1P3ybOuJbA+RRa8LSUkeaXguPwsvbFr027ZpBjnRUkro8PKvo5EFCgGHScp4+PnyWMeuGU/u1JKfy3a/oWnadNVA+6XEFiK28INLE7f3Ag1f46VQN1kQl37eLHnipw4tvpp2Rd5npnf5Rx0uBBSRK9yq9hDm28kKlHKRVoNGr1uf5x8Gph7zzb5gL6UTDaWaEYtgi6pccfS+C3RF+L7tVTN6uuCgkgcbie/SBuw+GmtefnmaFRGvFTx+ESdfIv2VipK+JdyRRtWZ/0I2x/C6J9VGf2fKx7iXD+IicSFnCZObkeh0jYgWZ7u2fzOm40m2cf4mr+SmDXNbPFEHupH7lFXRTS2ZBqRTt4MEcesgiwR4gu7g/RPDXXxMfNeEdB+VuOzkPd0q/ayFa46sIv6aKItbq7jvk8Wf7E7hF6z+EeTgKrN4A2StNqGnvw6bfDyF487spewdyrdOlfNKNiyX73boWD8kngKdqGnOWaccDwNh2uht3I+E+q8LRMEU0DceOAU4RdSxtOQz30DJ1KPa4KNwHzvH4HnRGH/M+v20jGzlcEYvHuvM0rbPz5Iv16mJlMyL0TdxUhFLqB9G1eLrE5l1+xXiPOXOz+VQYC/2MiSIYMNgEvKscQIgjKK6biQ+2JsDMKSeY9ULbYnUEHPx/CkjSnp4mp6EhpstljGJ/UBQ7+rAZGnrrU0GnNkRc+6tFaZvy+HZjp1HRRJ7DYN3uljst6IhPPiccramWZEDLilN+xTRBTCqYmAl0j6lZ5ZEsnhl+13uXANU/cBxa8vLwAXf28yrBv3MWusGEoeb0IsXuPidXU+ei1+a0iKR+TsWxlB3acb+vAMJqY/qFOq7QZMEBYJDqVta8zvyq6keOx04S+UzxRlROTrWvloZ9Q7rjk9+F/26ydW+8d/ZgxLJOl3xOv9f4gTlFY+D4qUBCa6k0R94+bi0Jhpe7LC4097KueK7cH/jISyY3EL++l7Z1g8kEyhNMf3tRtS05WYKkzo5Z0/M1oCQDJjlUMmWxhoCIuUcP5MzuX5Du61F2aC1vDjRSP/hx8gRQ0NK1DALN+lWAneMta4Uc7AAuassZF+SfGLyJcbsUpsfSry1ST0LWA6FDimvoDes5gkOsBZFpkcJIooe8tXdMKTx42kzEemIvWFtR/ZMLsmCxOfxLfgn7+s5I4qCYLsTzl0KDVlBMhxv2CJE5ITO5uzB0v02tLyoRrmRud8aKm+DuUFmdn1Jbzo7s80fD0C9SUCxXfVBDKUm9HgQsa91cOTSTQYwbpby/nXTwmNPDrqJhnTMK2tjccHoUtxG8Hc/Ue8EbeI6Rk4JplxrA8dV X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:OS9PR01MB13950.jpnprd01.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(52116014)(376014)(1800799024)(366016)(38350700014);DIR:OUT;SFP:1101; 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Tue, 25 Mar 2025 14:56:43 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/18351 Dear All, This patch series adds initial support for the Renesas RZ/G3E SoC and RZ/G3E SMARC EVK platform to linux-6.12.y-cip kernel. The RZ/G3E device is a general-purpose microprocessor with a quad-core CA-55, single core CM-33, Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals. All patches are cherry-picked from mainline kernel. base commit: be95b49207284 Add configuration for gitlab-ci. Test logs from linux-6.12.y-cip: root@smarc-rzg3e:~# uname -r 6.12.19-00045-gabf61442f552 root@smarc-rzg3e:~# cat /proc/cpuinfo processor : 0 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 processor : 1 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 processor : 2 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 processor : 3 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 root@smarc-rzg3e:~# cat /proc/meminfo MemTotal: 3883788 kB MemFree: 3565028 kB MemAvailable: 3499708 kB root@smarc-rzg3e:~# cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 11: 2780 2944 2562 2246 GICv3 27 Level arch_timer 14: 0 0 0 0 GICv3 561 Level 11c01400.serial:rx err 15: 1 0 0 0 GICv3 564 Level 11c01400.serial:rx full 16: 1524 0 0 0 GICv3 565 Level 11c01400.serial:tx empty 17: 0 0 0 0 GICv3 562 Level 11c01400.serial:break 18: 73 0 0 0 GICv3 566 Level 11c01400.serial:rx ready 19: 0 0 0 0 GICv3 563 Level 11c01400.serial:tx end IPI0: 225 437 170 261 Rescheduling interrupts IPI1: 2928 3415 1858 3132 Function call interrupts IPI2: 0 0 0 0 CPU stop interrupts IPI3: 0 0 0 0 CPU stop NMIs IPI4: 0 0 0 0 Timer broadcast interrupts IPI5: 278 353 190 188 IRQ work interrupts IPI6: 0 0 0 0 CPU backtrace interrupts IPI7: 0 0 0 0 KGDB roundup interrupts Err: 0 Thanks & Regards, Tommaso Biju Das (12): dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK dt-bindings: clock: renesas: Document RZ/G3E SoC CPG clk: renesas: rzv2h: Add MSTOP support clk: renesas: rzv2h: Add support for RZ/G3E SoC clk: renesas: r9a09g047: Add CA55 core clocks arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC arm64: dts: renesas: r9a09g047: Add OPP table arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board soc: renesas: Add RZ/G3E (R9A09G047) config option arm64: defconfig: Enable R9A09G047 SoC Fabrizio Castro (1): clk: renesas: r9a09g057: Add clock and reset entries for ICU Lad Prabhakar (3): clk: renesas: rzv2h: Add selective Runtime PM support for clocks clk: renesas: r9a09g057: Add CA55 core clocks clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets .../bindings/clock/renesas,rzv2h-cpg.yaml | 15 +- .../bindings/soc/renesas/renesas.yaml | 17 ++ arch/arm64/boot/dts/renesas/Makefile | 2 + arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 185 +++++++++++++++++ arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi | 18 ++ .../boot/dts/renesas/r9a09g047e57-smarc.dts | 18 ++ arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi | 13 ++ .../boot/dts/renesas/renesas-smarc2.dtsi | 24 +++ .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 28 +++ arch/arm64/configs/defconfig | 1 + drivers/clk/renesas/Kconfig | 7 +- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a09g047-cpg.c | 118 +++++++++++ drivers/clk/renesas/r9a09g057-cpg.c | 192 +++++++++++++---- drivers/clk/renesas/rzv2h-cpg.c | 196 +++++++++++++++--- drivers/clk/renesas/rzv2h-cpg.h | 44 +++- drivers/soc/renesas/Kconfig | 5 + .../dt-bindings/clock/renesas,r9a09g047-cpg.h | 21 ++ 18 files changed, 830 insertions(+), 75 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi create mode 100644 arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi create mode 100644 arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi create mode 100644 drivers/clk/renesas/r9a09g047-cpg.c create mode 100644 include/dt-bindings/clock/renesas,r9a09g047-cpg.h