[6.1.y-cip,00/43] Add RZ/G3E pinctrl support

Message

Tommaso Merciai March 31, 2025, 10:44 a.m. UTC

This patch series adds pin controller support for the Renesas RZ/G3E(R9A09G047)
SoC to linux-6.1.y-cip kernel, this series adds also device node for SCIF
pincontrol into RZ/G3E SMARC EVK board dts.
The RZ/G3E PFC (Pin Function Controller) is almost similar to the one found
into the RZ/V2H which is in turn similar to the one found into the RZ/G2L SoC,
for this reason pinctrl-rzg2l.c has been re-used.

All patches are cherry-picked from mainline kernel.

base commit: 609e6d99a3155 arm64: defconfig: Enable R9A09G047 SoC

Thanks & Regards,
Tommaso

Andy Shevchenko (1):
  pinctrl: renesas: rzg2l: Replace of_node_to_fwnode() with more
    suitable API

Biju Das (8):
  dt-bindings: pinctrl: renesas: Add alpha-numerical port support for
    RZ/V2H
  dt-bindings: pinctrl: renesas: Document RZ/G3E SoC
  pinctrl: renesas: rzg2l: Use dev_err_probe()
  pinctrl: renesas: rzg2l: Fix missing return in
    rzg2l_pinctrl_register()
  pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg table
  pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC
  arm64: dts: renesas: r9a09g047: Add pincontrol node
  arm64: dts: renesas: r9a09g047e57-smarc: Add SCIF pincontrol

Fabrizio Castro (1):
  pinctrl: renesas: rzg2l: Remove RZG2L_TINT_IRQ_START_INDEX

Kartik (1):
  mm/util: Introduce kmemdup_array()

Lad Prabhakar (28):
  dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow 'input' and
    'output-enable' properties
  dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Remove the check from the
    object
  dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoC
  dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow schmitt and open
    drain properties
  pinctrl: renesas: rzg2l: Allow more bits for pin configuration
  pinctrl: renesas: rzg2l: Drop struct rzg2l_variable_pin_cfg
  pinctrl: renesas: rzg2l: Enable variable configuration for all
  pinctrl: renesas: rzg2l: Validate power registers for SD and ETH
  pinctrl: renesas: rzg2l: Add function pointer for PFC register locking
  pinctrl: renesas: rzg2l: Add function pointer for PMC register write
  pinctrl: renesas: rzg2l: Add function pointers for OEN register access
  pinctrl: renesas: rzg2l: Add support to configure slew-rate
  pinctrl: renesas: rzg2l: Add support for pull-up/down
  pinctrl: renesas: rzg2l: Pass pincontrol device to
    pinconf_generic_parse_dt_config()
  pinctrl: renesas: rzg2l: Add support for custom parameters
  pinctrl: renesas: rzg2l: Acquire lock in rzg2l_pinctrl_pm_setup_pfc()
  pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC
  pinctrl: renesas: rzg2l: Update PIN_CFG_MASK() macro to be 32-bit wide
  pinctrl: renesas: rzg2l: Adjust bit masks for PIN_CFG_VARIABLE to use
    BIT(62)
  pinctrl: renesas: rzg2l: Move RZG2L_SINGLE_PIN definition to top of
    the file
  pinctrl: renesas: rzg2l: Reorganize variable configuration macro
  pinctrl: renesas: rzg2l: Return -EINVAL if the pin doesn't support
    PIN_CFG_OEN
  pinctrl: renesas: rzg2l: Introduce single macro for digital noise
    filter configuration
  pinctrl: renesas: rzg2l: Move pinconf_to_config_argument() call
    outside of switch cases
  pinctrl: renesas: rzg2l: Add support for enabling/disabling open-drain
    outputs
  pinctrl: renesas: rzg2l: Add support for configuring schmitt-trigger
  pinctrl: renesas: rzg2l: Use gpiochip_populate_parent_fwspec_twocell
    helper
  pinctrl: renesas: rzg2l: Fix PFC_MASK for RZ/V2H and RZ/G3E

Paul Barker (3):
  pinctrl: renesas: rzg2l: Clarify OEN read/write support
  pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write
    functions
  pinctrl: renesas: rzg2l: Support output enable on RZ/G2L

Shen Lichuan (1):
  pinctrl: renesas: Switch to use kmemdup_array()

 .../pinctrl/renesas,rzg2l-pinctrl.yaml        |   61 +-
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |   13 +
 .../boot/dts/renesas/r9a09g047e57-smarc.dts   |   13 +
 drivers/pinctrl/renesas/Kconfig               |    1 +
 drivers/pinctrl/renesas/pinctrl-rzg2l.c       | 1229 +++++++++++++----
 drivers/pinctrl/renesas/pinctrl-rzv2m.c       |    3 +-
 drivers/pinctrl/renesas/pinctrl.c             |    3 +-
 .../pinctrl/renesas,r9a09g047-pinctrl.h       |   41 +
 .../pinctrl/renesas,r9a09g057-pinctrl.h       |   31 +
 include/linux/string.h                        |    1 +
 mm/util.c                                     |   17 +
 11 files changed, 1103 insertions(+), 310 deletions(-)
 create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
 create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h

Comments

Pavel Machek April 1, 2025, 10:46 a.m. UTC | #1

Hi!

> This patch series adds pin controller support for the Renesas RZ/G3E(R9A09G047)
> SoC to linux-6.1.y-cip kernel, this series adds also device node for SCIF
> pincontrol into RZ/G3E SMARC EVK board dts.
> The RZ/G3E PFC (Pin Function Controller) is almost similar to the one found
> into the RZ/V2H which is in turn similar to the one found into the RZ/G2L SoC,
> for this reason pinctrl-rzg2l.c has been re-used.

I had some minor comments, but I can apply this to 6.1-cip provided it
compiles and there are no other comments.

Best regards,
								Pavel

Pavel Machek April 2, 2025, 8 a.m. UTC | #2

Hi!

> This patch series adds pin controller support for the Renesas RZ/G3E(R9A09G047)
> SoC to linux-6.1.y-cip kernel, this series adds also device node for SCIF
> pincontrol into RZ/G3E SMARC EVK board dts.
> The RZ/G3E PFC (Pin Function Controller) is almost similar to the one found
> into the RZ/V2H which is in turn similar to the one found into the RZ/G2L SoC,
> for this reason pinctrl-rzg2l.c has been re-used.
> 
> All patches are cherry-picked from mainline kernel.

Thank you, applied.

Best regards,
								Pavel