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Mon, 31 Mar 2025 11:07:20 +0000 From: Tommaso Merciai To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek CC: Biju Das , Lad Prabhakar , tomm.merciai@gmail.com Subject: [PATCH 6.12.y-cip 00/13] Add RZ/G3E pinctrl support Date: Mon, 31 Mar 2025 13:06:46 +0200 Message-ID: <20250331110659.252237-1-tommaso.merciai.xr@bp.renesas.com> X-Mailer: git-send-email 2.43.0 X-ClientProxiedBy: FR4P281CA0165.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:ba::20) To OS9PR01MB13950.jpnprd01.prod.outlook.com (2603:1096:604:35e::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OS9PR01MB13950:EE_|OS7PR01MB15065:EE_ X-MS-Office365-Filtering-Correlation-Id: dbbb09b7-ae2a-44b1-8848-08dd704434ac X-LD-Processed: 53d82571-da19-47e4-9cb4-625a166a4a2a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|52116014|376014|366016|38350700014; X-Microsoft-Antispam-Message-Info: aoiEaMQMrcx+vXWQ5ii+iCk0c6U21uhvSXA8j9VHkCYU4OYBb3pqrOPYQKVFOZlMYY07SDw7jae85/y0HnXukkeT7Ve1+1FHMW0Rpuv8DT9DHA+DzamMAdXnNR+sNhWAFJHyEHU1L+PFEvGoa/k8kLt6+prqbYrGXoy4+3wxnPnK2OzgAkfzs9vJX2bxXuGfEG4r1YaeLuPVgDqtiM+fvm6Ub6lgBs8odCNFxm4wdRxAK0fx3WJy0nFTW1sJ43xKjW6RpQcg/oaC1wRDvxEPSdPWByXSQgo2+G1Vw4qgl9hW4WrrsPIagvMopql0L+vmtT39oeyoNNu08cgEIKaNr/ZaFfWI5yyWnZCowbOSyPmS5w1LQWOOOIjFx15mPpbFPUtHUT+4IwSQVmlB+l7nMfQQLzuEGVwmuXwJrQcryrkDg8AqsQa3ojgN7NBplnzwt+cpxpphG3y3TGsIcHjAF0TvrjEgutNngLqEj3hwHKuAlCfnX+ohxc2jOQ2wnCaAzcQpoQDUE6iPB7Uwn6fXBQoeAMLKXdMS2NZo803WgLmekvvqZihDmBQzvoZ85F6+2vhEQReannyQAjD9KcMHQ7jQf+KHN9v/egH8VNvKLMOyMKpIqwpY05CEJTpF4VGEF6/w6jXRdwkiZLAVnH3zXIQg3SOfaorGO8qWYkPSkhw6HmTEnbQmaKYVVWLPsbmpIVgk2HRHk99X2SsKpD4LYLN8D9PboVqvGHZGrvedDmLOtmDTsAkI/wBSnOauElbwJBIcLEHcY5sxRE0SptdOGV5CySc5L+zaarc3Jpg5udWfX///vJPM5bGirK5tWWosCpngRsS2PB5hfAlVoSklGtllaB8U2fA4JCk0PoBvbpTaYh/VRYVcupzXU2upATSSdkl8Heht3L0i3rUhNKdS8KRquAobU5fhtTz4S9gQacJtTkrE1TeUpHXe2E/3hSe30BWC30EZetxqHc2IYEoNEke1SfD6UCbmeDnlHhN2bKitSgrNo/GGyIMEj/0R+/a59gbDvQptUOcTEnaUAnztN+hB3z+xvGsepwcJIcDBLm9s5bYGLF59gipjBt1+kSf5mBAIPaH0LBGzh3jOHzy/lTgDb34xzqwxQ29cT+58Qctr/P9z3ugXlkyVRg3Vw/9de7Iub1zSMHOlYw9HHD1MBKm+Zl43K9fUrQ816g8nN5XFoFZhpY9G1gBn1zcei9rSBJ0KsBCz+bl/61eXHZUlJOS4dp1iIp4+xWcZH/cGeO3oIdP3CK808nMVRyCtK325ZO9FhBnTjw0BgPzPXkdPjBe6/0VXIxVXimPdDDrWAEDwvRDblNaVJ6yuIufmqTENeurAuH4q75ZgL1ZI/OC1NLPQqD14SZgZJxWZXRvHkAbW724Eh+igyZZFYH0VBF3VpsXoHw0qqe2KmwQpZHij/wmzeEyTZ/eBHYLy0UaWwQY1fyQxcIaOTnsNDfXfdlE/ X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:OS9PR01MB13950.jpnprd01.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(52116014)(376014)(366016)(38350700014);DIR:OUT;SFP:1101; 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Mon, 31 Mar 2025 11:07:31 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/18432 This patch series adds pin controller support for the Renesas RZ/G3E(R9A09G047) SoC to linux-6.12.y-cip kernel, this series adds also device node for SCIF pincontrol into RZ/G3E SMARC EVK board dts. The RZ/G3E PFC (Pin Function Controller) is almost similar to the one found into the RZ/V2H which is in turn similar to the one found into the RZ/G2L SoC, for this reason pinctrl-rzg2l.c has been re-used. All patches are cherry-picked from mainline kernel. base commit: 5a8fa9a11dd1b arm64: defconfig: Enable R9A09G047 SoC Thanks & Regards, Tommaso Biju Das (6): dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H dt-bindings: pinctrl: renesas: Document RZ/G3E SoC pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg table pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC arm64: dts: renesas: r9a09g047: Add pincontrol node arm64: dts: renesas: r9a09g047e57-smarc: Add SCIF pincontrol Fabrizio Castro (1): pinctrl: renesas: rzg2l: Remove RZG2L_TINT_IRQ_START_INDEX Lad Prabhakar (6): dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoC dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow schmitt and open drain properties pinctrl: renesas: rzg2l: Move RZG2L_SINGLE_PIN definition to top of the file pinctrl: renesas: rzg2l: Add support for enabling/disabling open-drain outputs pinctrl: renesas: rzg2l: Add support for configuring schmitt-trigger pinctrl: renesas: rzg2l: Use gpiochip_populate_parent_fwspec_twocell helper .../pinctrl/renesas,rzg2l-pinctrl.yaml | 23 +- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 13 + .../boot/dts/renesas/r9a09g047e57-smarc.dts | 13 + drivers/pinctrl/renesas/Kconfig | 1 + drivers/pinctrl/renesas/pinctrl-rzg2l.c | 254 ++++++++++++++++-- .../pinctrl/renesas,r9a09g047-pinctrl.h | 41 +++ .../pinctrl/renesas,r9a09g057-pinctrl.h | 31 +++ 7 files changed, 351 insertions(+), 25 deletions(-) create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h