[09/18] arm64: defconfig: enable R8A774C0 SoC

Message ID	1553178256-6293-10-git-send-email-biju.das@bp.renesas.com (mailing list archive)
State	Accepted
Delegated to:	Pavel Machek
Headers	show Return-Path: <cip-dev-bounces@lists.cip-project.org> From: Biju Das <biju.das@bp.renesas.com> To: cip-dev@lists.cip-project.org Date: Thu, 21 Mar 2019 14:24:07 +0000 Message-Id: <1553178256-6293-10-git-send-email-biju.das@bp.renesas.com> In-Reply-To: <1553178256-6293-1-git-send-email-biju.das@bp.renesas.com> References: <1553178256-6293-1-git-send-email-biju.das@bp.renesas.com> Cc: Biju Das <biju.das@bp.renesas.com> Subject: [cip-dev] [PATCH 09/18] arm64: defconfig: enable R8A774C0 SoC Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org
Series	Add RZ/G2[ME] SoC Identification/SYSC/RST support \| expand [00/18] Add RZ/G2[ME] SoC Identification/SYSC/RST support [01/18] dt-bindings: arm: Document RZ/G2M SoC DT bindings [02/18] dt-bindings: arm: Document RZ/G2E SoC DT bindings [03/18] dt-bindings: arm: Fix RZ/G2E part number [04/18] soc: renesas: Identify RZ/G2M [05/18] soc: renesas: Identify RZ/G2E [06/18] arm64: Add Renesas R8A774A1 support [07/18] arm64: Add Renesas R8A774C0 support [08/18] arm64: defconfig: enable R8A774A1 SoC [09/18] arm64: defconfig: enable R8A774C0 SoC [10/18] dt-bindings: power: Add r8a774a1 SYSC power domain definitions [11/18] dt-bindings: power: Add r8a774c0 SYSC power domain definitions [12/18] soc: renesas: rcar-sysc: Add r8a774a1 support [13/18] dt-bindings: power: rcar-sysc: Document r8a774c0 sysc [14/18] soc: renesas: rcar-sysc: Add r8a774c0 support [15/18] soc: renesas: r8a774c0-sysc: Fix initialization order of 3DG-{A, B} [16/18] soc: renesas: rcar-rst: Add support for RZ/G2M [17/18] dt-bindings: reset: rcar-rst: Document r8a774c0 rst [18/18] soc: renesas: rcar-rst: Add support for RZ/G2E

Message ID

1553178256-6293-10-git-send-email-biju.das@bp.renesas.com (mailing list archive)

State

Accepted

Delegated to:

Pavel Machek

Headers

From: Biju Das <biju.das@bp.renesas.com>
To: cip-dev@lists.cip-project.org
Date: Thu, 21 Mar 2019 14:24:07 +0000
Message-Id: <1553178256-6293-10-git-send-email-biju.das@bp.renesas.com>
In-Reply-To: <1553178256-6293-1-git-send-email-biju.das@bp.renesas.com>
References: <1553178256-6293-1-git-send-email-biju.das@bp.renesas.com>
Cc: Biju Das <biju.das@bp.renesas.com>
Subject: [cip-dev] [PATCH 09/18] arm64: defconfig: enable R8A774C0 SoC
Precedence: list
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Sender: cip-dev-bounces@lists.cip-project.org
Errors-To: cip-dev-bounces@lists.cip-project.org

Series

Add RZ/G2[ME] SoC Identification/SYSC/RST support | expand

Commit Message

Biju Das March 21, 2019, 2:24 p.m. UTC

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Enable the Renesas RZ/G2E (R8A774C0) SoC in the ARM64 defconfig.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 76506880eac66cb1f189a993c39ad0fcba723b99)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 3f1868c..e6ec985 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -51,6 +51,7 @@  CONFIG_ARCH_SEATTLE=y
 CONFIG_ARCH_SYNQUACER=y
 CONFIG_ARCH_RENESAS=y
 CONFIG_ARCH_R8A774A1=y
+CONFIG_ARCH_R8A774C0=y
 CONFIG_ARCH_R8A7795=y
 CONFIG_ARCH_R8A7796=y
 CONFIG_ARCH_R8A77965=y

[09/18] arm64: defconfig: enable R8A774C0 SoC

Commit Message

Patch