diff mbox series

[4.4.y,42/52] ARM: dts: r8a77470: Add IRQC support

Message ID	1557761837-24993-43-git-send-email-fabrizio.castro@bp.renesas.com (mailing list archive)
State	Accepted
Headers	show Return-Path: <cip-dev-bounces@lists.cip-project.org> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com> To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:37:07 +0100 Message-Id: <1557761837-24993-43-git-send-email-fabrizio.castro@bp.renesas.com> In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das <biju.das@bp.renesas.com> Subject: [cip-dev] [PATCH 4.4.y 42/52] ARM: dts: r8a77470: Add IRQC support Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org
Series	Add basic support for the iwg23s \| expand [4.4.y,00/52] Add basic support for the iwg23s [4.4.y,01/52] ARM: shmobile: r8a77470: basic SoC support [4.4.y,02/52] clk: shmobile: rcar-gen2: Add quirks for the RZ/G1C [4.4.y,03/52] clk: shmobile: Compile clk-rcar-gen2.c when using the r8a77470 [4.4.y,04/52] ARM: shmobile: r8a77470: Add clock index macros for DT sources [4.4.y,05/52] pinctrl: sh-pfc: Add r8a77470 PFC support [4.4.y,06/52] pinctrl: sh-pfc: r8a77470: Add EtherAVB pin groups [4.4.y,07/52] pinctrl: sh-pfc: r8a77470: Add I2C4 pin groups [4.4.y,08/52] pinctrl: sh-pfc: r8a77470: Add DU0 pin groups [4.4.y,09/52] pinctrl: sh-pfc: r8a77470: Add QSPI0 pin groups [4.4.y,10/52] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups [4.4.y,11/52] pinctrl: sh-pfc: r8a77470: Add USB pin groups [4.4.y,12/52] pinctrl: sh-pfc: r8a77470: Add remaining I2C pin groups [4.4.y,13/52] pinctrl: sh-pfc: r8a77470: Add DU1 pin groups [4.4.y,14/52] pinctrl: sh-pfc: r8a77470: Add VIN pin groups [4.4.y,15/52] pinctrl: sh-pfc: r8a77470: Add QSPI1 pin groups [4.4.y,16/52] soc: renesas: rcar-rst: Add support for RZ/G1C [4.4.y,17/52] ARM: debug-ll: Add support for r8a77470 [4.4.y,18/52] gpiolib: Extract mask allocation into subroutine [4.4.y,19/52] gpiolib: Support 'gpio-reserved-ranges' property [4.4.y,20/52] gpiolib: Avoid calling chip->request() for unused gpios [4.4.y,21/52] gpio: rcar: Implement gpiochip.set_multiple() [4.4.y,22/52] gpio: rcar: Add GPIO hole support [4.4.y,23/52] dt-bindings: gpio: Add a gpio-reserved-ranges property [4.4.y,24/52] dt-bindings: gpio: rcar: Add gpio-reserved-ranges support [4.4.y,25/52] ARM: shmobile: defconfig: Enable r8a77470 SoC [4.4.y,26/52] ARM: multi_v7_defconfig: Enable r8a77470 SoC [4.4.y,27/52] serial: sh-sci: Document r8a77470 bindings [4.4.y,28/52] dt-bindings: sram: Document renesas, smp-sram [4.4.y,29/52] ARM: dts: r8a77470: Initial SoC device tree [4.4.y,30/52] clk: shmobile: Document r8a77470 CPG clock support [4.4.y,31/52] clk: shmobile: Document r8a77470 CPG DIV6 clock support [4.4.y,32/52] clk: shmobile: Document r8a77470 MSTP clock support [4.4.y,33/52] ARM: dts: r8a77470: Add clocks [4.4.y,34/52] dt-bindings: arm: Document iW-RainboW-G23S single board computer [4.4.y,35/52] ARM: dts: iwg23s-sbc: Add support for iWave G23S-SBC based on RZ/G1C [4.4.y,36/52] dt-bindings: pinctrl: sh-pfc: Document r8a77470 PFC support [4.4.y,37/52] ARM: dts: r8a77470: Add PFC support [4.4.y,38/52] dt-bindings: gpio: rcar: Add r8a77470 (RZ/G1C) support [4.4.y,39/52] ARM: dts: r8a77470: Add GPIO support [4.4.y,40/52] ARM: dts: r8a77470: Add SCIF support [4.4.y,41/52] dt-bindings: irqchip: renesas-irqc: Document r8a77470 support [4.4.y,42/52] ARM: dts: r8a77470: Add IRQC support [4.4.y,43/52] ARM: dts: iwg23s-sbc: Add pinctl support for scif1 [4.4.y,44/52] dt-bindings: rcar-dmac: Document missing error interrupt [4.4.y,45/52] dt-bindings: rcar-dmac: Document r8a77470 support [4.4.y,46/52] ARM: dts: r8a77470: Add SYS-DMAC support [4.4.y,47/52] ARM: dts: r8a77470: Add SCIF DMA support [4.4.y,48/52] dt-bindings: net: renesas-ravb: Add support for r8a77470 SoC [4.4.y,49/52] ARM: dts: r8a77470: Add EtherAVB support [4.4.y,50/52] ARM: dts: iwg23s-sbc: Add EtherAVB support [4.4.y,51/52] ARM: dts: iwg23s-sbc: specify EtherAVB PHY IRQ [4.4.y,52/52] ARM: dts: iwg23s-sbc: Add pinctl support for EtherAVB

Commit Message

Fabrizio Castro May 13, 2019, 3:37 p.m. UTC

From: Biju Das <biju.das@bp.renesas.com>

commit 141fb10294e3ba5ee2d34d464ddc8a9952bd3372 upstream.

Describe the IRQC interrupt controller in the R8A77470 device tree.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
[fab: reworked clocks and power-domains properties. Removed resets
property]
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm/boot/dts/r8a77470.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff mbox series

Patch

diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 2d542b3..1325dae 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -154,6 +154,25 @@ 
 			reg = <0 0xe6160000 0 0x100>;
 		};
 
+		irqc: interrupt-controller@e61c0000 {
+			compatible = "renesas,irqc-r8a77470", "renesas,irqc";
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			reg = <0 0xe61c0000 0 0x200>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&mstp4_clks R8A77470_CLK_IRQC>;
+			power-domains = <&cpg_clocks>;
+		};
+
 		icram0:	sram@e63a0000 {
 			compatible = "mmio-sram";
 			reg = <0 0xe63a0000 0 0x12000>;