From patchwork Mon Jul 15 13:29:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11044067 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8C6301395 for ; Mon, 15 Jul 2019 13:35:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7B74E1FE95 for ; Mon, 15 Jul 2019 13:35:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6F06D2841F; Mon, 15 Jul 2019 13:35:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id ED1791FE95 for ; Mon, 15 Jul 2019 13:35:54 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 3448CDCB; Mon, 15 Jul 2019 13:35:42 +0000 (UTC) X-Original-To: cip-dev@lists.cip-project.org Delivered-To: cip-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 93D70DB8 for ; Mon, 15 Jul 2019 13:35:40 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id CA5F6876 for ; Mon, 15 Jul 2019 13:35:39 +0000 (UTC) X-IronPort-AV: E=Sophos;i="5.62,493,1554735600"; d="scan'208";a="21445277" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 15 Jul 2019 22:35:39 +0900 Received: from be1yocto.ree.adwin.renesas.com (unknown [172.29.43.62]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 8944E4237F7E; Mon, 15 Jul 2019 22:35:38 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org Date: Mon, 15 Jul 2019 14:29:49 +0100 Message-Id: <1563197408-59548-5-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563197408-59548-1-git-send-email-biju.das@bp.renesas.com> References: <1563197408-59548-1-git-send-email-biju.das@bp.renesas.com> MIME-Version: 1.0 Cc: Biju Das Subject: [cip-dev] [PATCH 4.19.y-cip 04/23] clk: renesas: rcar-gen3: Add HS400 quirk for SD clock X-BeenThere: cip-dev@lists.cip-project.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Niklas Söderlund commit 36c4da4f552a126bb29a95dc5c9608795491e32a upstream. On H3 (ES1.x, ES2.0) and M3-W (ES1.0, ES1.1) the clock setting for HS400 needs a quirk to function properly. The reason for the quirk is that there are two settings which produces same divider value for the SDn clock. On the effected boards the one currently selected results in HS400 not working. This change uses the same method as the Gen2 CPG driver and simply ignores the first clock setting as this is the offending one when selecting the settings. Which of the two possible settings is used have no effect for SDR104. Signed-off-by: Niklas Söderlund Tested-by: Wolfram Sang Acked-by: Wolfram Sang Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- drivers/clk/renesas/rcar-gen3-cpg.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 00e41de..3ba5076 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -245,6 +245,10 @@ struct sd_clock { * 1 0 2 (4) 0 (2) 8 * 1 0 3 (8) 0 (2) 16 * 1 0 4 (16) 0 (2) 32 + * + * NOTE: There is a quirk option to ignore the first row of the dividers + * table when searching for suitable settings. This is because HS400 on + * early ES versions of H3 and M3-W requires a specific setting to work. */ static const struct sd_div_table cpg_sd_div_table[] = { /* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */ @@ -355,6 +359,12 @@ static const struct clk_ops cpg_sd_clock_ops = { .set_rate = cpg_sd_clock_set_rate, }; +static u32 cpg_quirks __initdata; + +#define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */ +#define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */ +#define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */ + static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core, void __iomem *base, const char *parent_name, struct raw_notifier_head *notifiers) @@ -380,6 +390,11 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core, clock->div_table = cpg_sd_div_table; clock->div_num = ARRAY_SIZE(cpg_sd_div_table); + if (cpg_quirks & SD_SKIP_FIRST) { + clock->div_table++; + clock->div_num--; + } + val = readl(clock->csn.reg) & ~CPG_SD_FC_MASK; val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK); writel(val, clock->csn.reg); @@ -407,23 +422,27 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core, static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata; static unsigned int cpg_clk_extalr __initdata; static u32 cpg_mode __initdata; -static u32 cpg_quirks __initdata; - -#define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */ -#define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */ static const struct soc_device_attribute cpg_quirks_match[] __initconst = { { .soc_id = "r8a7795", .revision = "ES1.0", - .data = (void *)(PLL_ERRATA | RCKCR_CKSEL), + .data = (void *)(PLL_ERRATA | RCKCR_CKSEL | SD_SKIP_FIRST), }, { .soc_id = "r8a7795", .revision = "ES1.*", - .data = (void *)RCKCR_CKSEL, + .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST), + }, + { + .soc_id = "r8a7795", .revision = "ES2.0", + .data = (void *)SD_SKIP_FIRST, }, { .soc_id = "r8a7796", .revision = "ES1.0", - .data = (void *)RCKCR_CKSEL, + .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST), + }, + { + .soc_id = "r8a7796", .revision = "ES1.1", + .data = (void *)SD_SKIP_FIRST, }, { /* sentinel */ } };