[4.4.y-cip,09/17] ARM: dts: r8a7744: Add [H]SCIF{A|B} support

Message ID	1574175222-52858-10-git-send-email-biju.das@bp.renesas.com (mailing list archive)
State	Accepted
Delegated to:	Nobuhiro Iwamatsu
Headers	show Return-Path: <SRS0=KYNi=ZL=lists.cip-project.org=cip-dev-bounces@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0382D222A0 From: Biju Das <biju.das@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> Date: Tue, 19 Nov 2019 14:53:34 +0000 Message-Id: <1574175222-52858-10-git-send-email-biju.das@bp.renesas.com> In-Reply-To: <1574175222-52858-1-git-send-email-biju.das@bp.renesas.com> References: <1574175222-52858-1-git-send-email-biju.das@bp.renesas.com> Cc: Biju Das <biju.das@bp.renesas.com> Subject: [cip-dev] [PATCH 4.4.y-cip 09/17] ARM: dts: r8a7744: Add [H]SCIF{A\|B} support Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: cip-dev-bounces@lists.cip-project.org Sender: "cip-dev" <cip-dev-bounces@lists.cip-project.org>
Series	Add SYS-DMAC/GPIO/AVB/SMP/SCIF/HSCIF/I2C/IIC/CMT/RWDT support \| expand [4.4.y-cip,00/17] Add SYS-DMAC/GPIO/AVB/SMP/SCIF/HSCIF/I2C/IIC/CMT/RWDT support [4.4.y-cip,01/17] dt-bindings: rcar-dmac: Document r8a7744 support [4.4.y-cip,02/17] ARM: dts: r8a7744: Add SYS-DMAC support [4.4.y-cip,03/17] dt-bindings: gpio: rcar: Add r8a7744 (RZ/G1N) support [4.4.y-cip,04/17] ARM: dts: r8a7744: Add GPIO support [4.4.y-cip,05/17] dt-bindings: net: ravb: Add support for r8a7744 SoC [4.4.y-cip,06/17] ARM: dts: r8a7744: Add Ethernet AVB support [4.4.y-cip,07/17] dt-bindings: apmu: Document r8a7744 support [4.4.y-cip,08/17] ARM: dts: r8a7744: Add SMP support [4.4.y-cip,09/17] ARM: dts: r8a7744: Add [H]SCIF{A\|B} support [4.4.y-cip,10/17] dt-bindings: i2c: rcar: Document r8a7744 support [4.4.y-cip,11/17] dt-bindings: i2c: sh_mobile: Document r8a7744 support [4.4.y-cip,12/17] ARM: dts: r8a7744: Add I2C and IIC support [4.4.y-cip,13/17] dt-bindings: timer: renesas, cmt: Document r8a7744 CMT [4.4.y-cip,14/17] ARM: dts: r8a7744: Add CMT SoC specific support [4.4.y-cip,15/17] dt-bindings: watchdog: renesas-wdt: Document r8a7744 support [4.4.y-cip,16/17] ARM: dts: r8a7744: Add RWDT node [4.4.y-cip,17/17] ARM: dts: iwg20d-q7-common: Move cmt/rwdt node out of RZ/G1M SOM

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index e712b13..fdfd099 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -386,9 +386,130 @@ status = "disabled"; }; + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7744", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7744_CLK_SCIFA0>; + clock-names = "sci_ick"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7744", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7744_CLK_SCIFA1>; + clock-names = "sci_ick"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7744", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 0x40>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7744_CLK_SCIFA2>; + clock-names = "sci_ick"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7744", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 0x40>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7744_CLK_SCIFA3>; + clock-names = "sci_ick"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7744", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 0x40>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7744_CLK_SCIFA4>; + clock-names = "sci_ick"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7744", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 0x40>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7744_CLK_SCIFA5>; + clock-names = "sci_ick"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7744", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7744_CLK_SCIFB0>; + clock-names = "sci_ick"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7744", + "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c30000 0 0x100>; - /* placeholder */ + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7744_CLK_SCIFB1>; + clock-names = "sci_ick"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7744", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7744_CLK_SCIFB2>; + clock-names = "sci_ick"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; }; scif0: serial@e6e60000 { @@ -399,18 +520,131 @@ clocks = <&mstp7_clks R8A7744_CLK_SCIF0>, <&zs_clk>, <&scif_clk>; clock-names = "sci_ick", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&cpg_clocks>; status = "disabled"; }; scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7744", + "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e68000 0 0x40>; - /* placeholder */ + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7744_CLK_SCIF1>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7744", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 0x40>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7744_CLK_SCIF2>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7744", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 0x40>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7744_CLK_SCIF3>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7744", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 0x40>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7744_CLK_SCIF4>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7744", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 0x40>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7744_CLK_SCIF5>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7744", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7744_CLK_HSCIF0>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; }; hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7744", + "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 0x60>; - /* placeholder */ + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7744_CLK_HSCIF1>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7744", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 0x60>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7744_CLK_HSCIF2>, + <&zs_clk>, <&scif_clk>; + clock-names = "sci_ick", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; }; can0: can@e6e80000 {

[4.4.y-cip,09/17] ARM: dts: r8a7744: Add [H]SCIF{A|B} support

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