diff mbox series

[5.10.y-cip,23/26] arm64: defconfig: Enable ARCH_R9A07G043

Message ID	20220831164645.2134258-24-biju.das.jz@bp.renesas.com (mailing list archive)
State	Accepted
Delegated to:	Pavel Machek
Headers	show Return-Path: <biju.das.jz@bp.renesas.com> ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) From: Biju Das <biju.das.jz@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> Cc: Chris Paterson <chris.paterson2@renesas.com>, Biju Das <biju.das.jz@bp.renesas.com>, Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: [PATCH 5.10.y-cip 23/26] arm64: defconfig: Enable ARCH_R9A07G043 Date: Wed, 31 Aug 2022 17:46:42 +0100 Message-Id: <20220831164645.2134258-24-biju.das.jz@bp.renesas.com> In-Reply-To: <20220831164645.2134258-1-biju.das.jz@bp.renesas.com> References: <20220831164645.2134258-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add RZ/G2UL support \| expand [5.10.y-cip,00/26] Add RZ/G2UL support [5.10.y-cip,01/26] dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions [5.10.y-cip,02/26] soc: renesas: Identify RZ/G2UL SoC [5.10.y-cip,03/26] clk: renesas: Add support for RZ/G2UL SoC [5.10.y-cip,04/26] clk: renesas: r9a07g043: Add GPIO clock and reset entries [5.10.y-cip,05/26] clk: renesas: r9a07g043: Add ethernet clock sources [5.10.y-cip,06/26] clk: renesas: r9a07g043: Add GbEthernet clock/reset [5.10.y-cip,07/26] clk: renesas: r9a07g043: Add SDHI clock and reset entries [5.10.y-cip,08/26] clk: renesas: r9a07g043: Add I2C clocks/resets [5.10.y-cip,09/26] clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries [5.10.y-cip,10/26] clk: renesas: r9a07g043: Add USB clocks/resets [5.10.y-cip,11/26] clk: renesas: r9a07g043: Add clock and reset entries for CANFD [5.10.y-cip,12/26] clk: renesas: r9a07g043: Add OSTM clock and reset entries [5.10.y-cip,13/26] clk: renesas: r9a07g043: Add WDT clock and reset entries [5.10.y-cip,14/26] pinctrl: renesas: rzg2l: Add RZ/G2UL support [5.10.y-cip,15/26] pinctrl: renesas: rzg2l: Restore pin config order [5.10.y-cip,16/26] pinctrl: renesas: rzg2l: Return -EINVAL for pins which have input disabled [5.10.y-cip,17/26] arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC [5.10.y-cip,18/26] arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK [5.10.y-cip,19/26] arm64: dts: renesas: r9a07g043: Fillup the pinctrl stub node [5.10.y-cip,20/26] arm64: dts: renesas: rzg2ul-smarc: Add scif0 and audio clk pins [5.10.y-cip,21/26] arm64: dts: renesas: r9a07g043: Add SDHI nodes [5.10.y-cip,22/26] arm64: dts: renesas: r9a07g043: Add GbEthernet nodes [5.10.y-cip,23/26] arm64: defconfig: Enable ARCH_R9A07G043 [5.10.y-cip,24/26] arm64: dts: renesas: rzg2ul-smarc: Enable microSD on SMARC platform [5.10.y-cip,25/26] arm64: dts: renesas: rzg2ul-smarc-som: Enable eMMC on SMARC platform [5.10.y-cip,26/26] arm64: dts: renesas: rzg2ul-smarc-som: Enable Ethernet on SMARC platform

Commit Message

Biju Das Aug. 31, 2022, 4:46 p.m. UTC

commit 5c40b3ba9e9de22cc5c6a1edef54e4ec52fcf845 upstream.

Enable support for the Renesas RZ/G2UL SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220423130206.114032-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff mbox series

Patch

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 7975a4b6a84a..1f1b96906f38 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -962,6 +962,7 @@  CONFIG_ARCH_R8A77970=y
 CONFIG_ARCH_R8A77980=y
 CONFIG_ARCH_R8A77990=y
 CONFIG_ARCH_R8A77995=y
+CONFIG_ARCH_R9A07G043=y
 CONFIG_ARCH_R9A07G044=y
 CONFIG_ARCH_R9A07G054=y
 CONFIG_ROCKCHIP_PM_DOMAINS=y