[5.10.y-cip,02/26] soc: renesas: Identify RZ/G2UL SoC

Message ID	20220831164645.2134258-3-biju.das.jz@bp.renesas.com (mailing list archive)
State	Accepted
Delegated to:	Pavel Machek
Headers	show Return-Path: <biju.das.jz@bp.renesas.com> ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) From: Biju Das <biju.das.jz@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> Cc: Chris Paterson <chris.paterson2@renesas.com>, Biju Das <biju.das.jz@bp.renesas.com>, Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: [PATCH 5.10.y-cip 02/26] soc: renesas: Identify RZ/G2UL SoC Date: Wed, 31 Aug 2022 17:46:21 +0100 Message-Id: <20220831164645.2134258-3-biju.das.jz@bp.renesas.com> In-Reply-To: <20220831164645.2134258-1-biju.das.jz@bp.renesas.com> References: <20220831164645.2134258-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add RZ/G2UL support \| expand [5.10.y-cip,00/26] Add RZ/G2UL support [5.10.y-cip,01/26] dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions [5.10.y-cip,02/26] soc: renesas: Identify RZ/G2UL SoC [5.10.y-cip,03/26] clk: renesas: Add support for RZ/G2UL SoC [5.10.y-cip,04/26] clk: renesas: r9a07g043: Add GPIO clock and reset entries [5.10.y-cip,05/26] clk: renesas: r9a07g043: Add ethernet clock sources [5.10.y-cip,06/26] clk: renesas: r9a07g043: Add GbEthernet clock/reset [5.10.y-cip,07/26] clk: renesas: r9a07g043: Add SDHI clock and reset entries [5.10.y-cip,08/26] clk: renesas: r9a07g043: Add I2C clocks/resets [5.10.y-cip,09/26] clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries [5.10.y-cip,10/26] clk: renesas: r9a07g043: Add USB clocks/resets [5.10.y-cip,11/26] clk: renesas: r9a07g043: Add clock and reset entries for CANFD [5.10.y-cip,12/26] clk: renesas: r9a07g043: Add OSTM clock and reset entries [5.10.y-cip,13/26] clk: renesas: r9a07g043: Add WDT clock and reset entries [5.10.y-cip,14/26] pinctrl: renesas: rzg2l: Add RZ/G2UL support [5.10.y-cip,15/26] pinctrl: renesas: rzg2l: Restore pin config order [5.10.y-cip,16/26] pinctrl: renesas: rzg2l: Return -EINVAL for pins which have input disabled [5.10.y-cip,17/26] arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC [5.10.y-cip,18/26] arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK [5.10.y-cip,19/26] arm64: dts: renesas: r9a07g043: Fillup the pinctrl stub node [5.10.y-cip,20/26] arm64: dts: renesas: rzg2ul-smarc: Add scif0 and audio clk pins [5.10.y-cip,21/26] arm64: dts: renesas: r9a07g043: Add SDHI nodes [5.10.y-cip,22/26] arm64: dts: renesas: r9a07g043: Add GbEthernet nodes [5.10.y-cip,23/26] arm64: defconfig: Enable ARCH_R9A07G043 [5.10.y-cip,24/26] arm64: dts: renesas: rzg2ul-smarc: Enable microSD on SMARC platform [5.10.y-cip,25/26] arm64: dts: renesas: rzg2ul-smarc-som: Enable eMMC on SMARC platform [5.10.y-cip,26/26] arm64: dts: renesas: rzg2ul-smarc-som: Enable Ethernet on SMARC platform

Message ID

20220831164645.2134258-3-biju.das.jz@bp.renesas.com (mailing list archive)

State

Accepted

Delegated to:

Pavel Machek

Headers

From: Biju Das <biju.das.jz@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Chris Paterson <chris.paterson2@renesas.com>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 5.10.y-cip 02/26] soc: renesas: Identify RZ/G2UL SoC
Date: Wed, 31 Aug 2022 17:46:21 +0100
Message-Id: <20220831164645.2134258-3-biju.das.jz@bp.renesas.com>
In-Reply-To: <20220831164645.2134258-1-biju.das.jz@bp.renesas.com>
References: <20220831164645.2134258-1-biju.das.jz@bp.renesas.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit

Series

Add RZ/G2UL support | expand

Commit Message

Biju Das Aug. 31, 2022, 4:46 p.m. UTC

commit 2f89bef90de4740be33b2cb4ba95e0107df0d25e upstream.

Add support for identifying the RZ/G2UL SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220315142644.17660-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/soc/renesas/Kconfig       |  6 ++++++
 drivers/soc/renesas/renesas-soc.c | 13 +++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index cf695f624d79..e0456af63d08 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -284,6 +284,12 @@  config ARCH_R8A774B1
 	help
 	  This enables support for the Renesas RZ/G2N SoC.
 
+config ARCH_R9A07G043
+	bool "ARM64 Platform support for RZ/G2UL"
+	select ARCH_RZG2L
+	help
+	  This enables support for the Renesas RZ/G2UL SoC variants.
+
 config ARCH_R9A07G044
 	bool "ARM64 Platform support for RZ/G2L"
 	select ARCH_RZG2L
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index 1ab78deaa239..70e5b7c2fc8b 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -60,6 +60,10 @@  static const struct renesas_family fam_rzg2l __initconst __maybe_unused = {
 	.name	= "RZ/G2L",
 };
 
+static const struct renesas_family fam_rzg2ul __initconst __maybe_unused = {
+	.name	= "RZ/G2UL",
+};
+
 static const struct renesas_family fam_rzv2l __initconst __maybe_unused = {
 	.name	= "RZ/V2L",
 };
@@ -144,6 +148,11 @@  static const struct renesas_soc soc_rz_g2l __initconst __maybe_unused = {
 	.id     = 0x841c447,
 };
 
+static const struct renesas_soc soc_rz_g2ul __initconst __maybe_unused = {
+	.family = &fam_rzg2ul,
+	.id     = 0x8450447,
+};
+
 static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused = {
 	.family = &fam_rzv2l,
 	.id     = 0x8447447,
@@ -317,6 +326,9 @@  static const struct of_device_id renesas_socs[] __initconst = {
 #ifdef CONFIG_ARCH_R8A779A0
 	{ .compatible = "renesas,r8a779a0",	.data = &soc_rcar_v3u },
 #endif
+#if defined(CONFIG_ARCH_R9A07G043)
+	{ .compatible = "renesas,r9a07g043",	.data = &soc_rz_g2ul },
+#endif
 #if defined(CONFIG_ARCH_R9A07G044)
 	{ .compatible = "renesas,r9a07g044",	.data = &soc_rz_g2l },
 #endif
@@ -355,6 +367,7 @@  static const struct renesas_id id_prr __initconst = {
 
 static const struct of_device_id renesas_ids[] __initconst = {
 	{ .compatible = "renesas,bsid",			.data = &id_bsid },
+	{ .compatible = "renesas,r9a07g043-sysc",	.data = &id_rzg2l },
 	{ .compatible = "renesas,r9a07g044-sysc",	.data = &id_rzg2l },
 	{ .compatible = "renesas,r9a07g054-sysc",	.data = &id_rzg2l },
 	{ .compatible = "renesas,prr",			.data = &id_prr },

[5.10.y-cip,02/26] soc: renesas: Identify RZ/G2UL SoC

Commit Message

Patch