From patchwork Wed Aug 31 16:46:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12961056 X-Patchwork-Delegate: pavel@denx.de Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82885ECAAD4 for ; Wed, 31 Aug 2022 16:47:07 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web10.1223.1661964417858439900 for ; Wed, 31 Aug 2022 09:47:04 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="5.93,278,1654527600"; d="scan'208";a="133251653" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 01 Sep 2022 01:47:03 +0900 Received: from localhost.localdomain (unknown [10.226.92.133]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id EE6BE40457CD; Thu, 1 Sep 2022 01:47:00 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH 5.10.y-cip 04/26] clk: renesas: r9a07g043: Add GPIO clock and reset entries Date: Wed, 31 Aug 2022 17:46:23 +0100 Message-Id: <20220831164645.2134258-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220831164645.2134258-1-biju.das.jz@bp.renesas.com> References: <20220831164645.2134258-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 31 Aug 2022 16:47:07 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/9364 commit 6c185664b3d481292c41fbfe66ea19c84cb0237a upstream. Add GPIO clock and reset entries in CPG driver. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220402074626.25624-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- drivers/clk/renesas/r9a07g043-cpg.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 81409ff37e2e..0c574e153d4d 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -112,6 +112,8 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x588, 0), DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0, 0x588, 1), + DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK, + 0x598, 0), }; static struct rzg2l_reset r9a07g043_resets[] = { @@ -127,6 +129,9 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4), DEF_RST(R9A07G043_SCI0_RST, 0x888, 0), DEF_RST(R9A07G043_SCI1_RST, 0x888, 1), + DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0), + DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1), + DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2), }; static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {