From patchwork Fri Sep 2 09:44:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12963976 X-Patchwork-Delegate: pavel@denx.de Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 003D7C38145 for ; Fri, 2 Sep 2022 09:45:28 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.4758.1662111901797907608 for ; Fri, 02 Sep 2022 02:45:19 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="5.93,283,1654527600"; d="scan'208";a="131461013" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 02 Sep 2022 18:45:19 +0900 Received: from localhost.localdomain (unknown [10.226.92.155]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 18C34400CF08; Fri, 2 Sep 2022 18:45:16 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH 5.10.y-cip 19/25] arm64: dts: renesas: r9a07g043: Add OPP table Date: Fri, 2 Sep 2022 10:44:21 +0100 Message-Id: <20220902094427.116227-20-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220902094427.116227-1-biju.das.jz@bp.renesas.com> References: <20220902094427.116227-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 02 Sep 2022 09:45:28 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/9445 commit e6a9acc370c6cb9e6ff6225b034a7a4374df0134 upstream. Add OPP table for RZ/G2UL SoC. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220501112926.47024-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 82fe61991204..e2300d5c6a15 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -42,6 +42,33 @@ extal_clk: extal-clk { clock-frequency = <0>; }; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -53,6 +80,7 @@ cpu0: cpu@0 { next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 {