[5.10.y-cip,31/33] pinctrl: renesas: Select PINCTRL_RZG2L if ARCH_RZG2L is enabled

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Biju Das <biju.das.jz@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Chris Paterson <chris.paterson2@renesas.com>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Subject: [PATCH 5.10.y-cip 31/33] pinctrl: renesas: Select PINCTRL_RZG2L if
 ARCH_RZG2L is enabled
Date: Fri, 21 Apr 2023 08:17:27 +0100
Message-Id: <20230421071729.130347-32-biju.das.jz@bp.renesas.com>
In-Reply-To: <20230421071729.130347-1-biju.das.jz@bp.renesas.com>
References: <20230421071729.130347-1-biju.das.jz@bp.renesas.com>
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Message ID	20230421071729.130347-32-biju.das.jz@bp.renesas.com (mailing list archive)
State	Accepted
Headers	show Return-Path: <biju.das.jz@bp.renesas.com> ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) From: Biju Das <biju.das.jz@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> Cc: Chris Paterson <chris.paterson2@renesas.com>, Biju Das <biju.das.jz@bp.renesas.com>, Fabrizio Castro <fabrizio.castro.jz@renesas.com> Subject: [PATCH 5.10.y-cip 31/33] pinctrl: renesas: Select PINCTRL_RZG2L if ARCH_RZG2L is enabled Date: Fri, 21 Apr 2023 08:17:27 +0100 Message-Id: <20230421071729.130347-32-biju.das.jz@bp.renesas.com> In-Reply-To: <20230421071729.130347-1-biju.das.jz@bp.renesas.com> References: <20230421071729.130347-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add RZ/V2M support \| expand [5.10.y-cip,00/33] Add RZ/V2M support [5.10.y-cip,01/33] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings [5.10.y-cip,02/33] dt-bindings: serial: renesas,em-uart: Add RZ/V2M clock to access the registers [5.10.y-cip,03/33] serial: 8250: extend compile-test coverage [5.10.y-cip,04/33] serial: 8250: SERIAL_8250_EM should depend on ARCH_RENESAS [5.10.y-cip,05/33] serial: 8250: Make SERIAL_8250_EM available for arm64 systems [5.10.y-cip,06/33] dt-bindings: arm: renesas: Document Renesas RZ/V2M SoC and EVK board [5.10.y-cip,07/33] dt-bindings: arm: renesas: Document Renesas RZ/V2M System Configuration [5.10.y-cip,08/33] soc: renesas: Identify RZ/V2M SoC [5.10.y-cip,09/33] soc: renesas: Add RZ/V2M (R9A09G011) config option [5.10.y-cip,10/33] arm64: defconfig: Enable Renesas RZ/V2M SoC [5.10.y-cip,11/33] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions [5.10.y-cip,12/33] dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC [5.10.y-cip,13/33] clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro [5.10.y-cip,14/33] clk: renesas: rzg2l: Add read only versions of the clk macros [5.10.y-cip,15/33] clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers [5.10.y-cip,16/33] clk: renesas: rzg2l: Make use of CLK_MON registers optional [5.10.y-cip,17/33] clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg [5.10.y-cip,18/33] clk: renesas: Add RZ/V2M support using the rzg2l driver [5.10.y-cip,19/33] clk: renesas: r9a09g011: Add eth clock and reset entries [5.10.y-cip,20/33] arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC [5.10.y-cip,21/33] arm64: dts: renesas: Add initial device tree for RZ/V2M EVK [5.10.y-cip,22/33] dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC [5.10.y-cip,23/33] ravb: Separate handling of irq enable/disable regs into feature [5.10.y-cip,24/33] ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs [5.10.y-cip,25/33] ravb: Use separate clock for gPTP [5.10.y-cip,26/33] ravb: Add support for RZ/V2M [5.10.y-cip,27/33] arm64: dts: renesas: r9a09g011: Add ethernet nodes [5.10.y-cip,28/33] arm64: dts: renesas: rzv2mevk2: Enable ethernet [5.10.y-cip,29/33] clk: renesas: r9a09g011: Add PFC clock and reset entries [5.10.y-cip,30/33] dt-bindings: pinctrl: Add DT bindings for Renesas RZ/V2M pinctrl [5.10.y-cip,31/33] pinctrl: renesas: Select PINCTRL_RZG2L if ARCH_RZG2L is enabled [5.10.y-cip,32/33] pinctrl: renesas: Add RZ/V2M pin and gpio controller driver [5.10.y-cip,33/33] arm64: dts: renesas: r9a09g011: Add pinctrl node

[5.10.y-cip,31/33] pinctrl: renesas: Select PINCTRL_RZG2L if ARCH_RZG2L is enabled

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