[RFC,11/30] riscv: dma-mapping: skip invalidation before bidirectional DMA

Commit Message

Lad Prabhakar Dec. 20, 2023, 11:06 p.m. UTC

From: Arnd Bergmann <[e-mail]>

commit 482069ebdc1d61fba14527055894b9f4f0ced08c upstream.

For a DMA_BIDIRECTIONAL transfer, the caches have to be cleaned
first to let the device see data written by the CPU, and invalidated
after the transfer to let the CPU see data written by the device.

riscv also invalidates the caches before the transfer, which does
not appear to serve any purpose.

Signed-off-by: Arnd Bergmann <[e-mail]>
Reviewed-by: Conor Dooley <[e-mail]>
Reviewed-by: Lad Prabhakar <[e-mail]>
Acked-by: Palmer Dabbelt <[e-mail]>
Acked-by: Guo Ren <[e-mail]>
Signed-off-by: Lad Prabhakar <[e-mail]>
Link: https://lore.kernel.org/r/[e-mail]
Signed-off-by: Palmer Dabbelt <[e-mail]>
Signed-off-by: Lad Prabhakar <[e-mail]>
---
 arch/riscv/mm/dma-noncoherent.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Patch

diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index 94614cf61cdd..fc6377a64c8d 100644
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -25,7 +25,7 @@  void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
 		ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
 		break;
 	case DMA_BIDIRECTIONAL:
-		ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
+		ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
 		break;
 	default:
 		break;