From patchwork Wed Dec 20 23:06:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 13500760 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AD96C46CD4 for ; Wed, 20 Dec 2023 23:07:34 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web11.34662.1703113653753344819 for ; Wed, 20 Dec 2023 15:07:33 -0800 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.04,292,1695654000"; d="scan'208";a="187185291" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 21 Dec 2023 08:07:33 +0900 Received: from Ubuntu-22.. (unknown [10.226.93.50]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 83D1840BF9EC; Thu, 21 Dec 2023 08:07:31 +0900 (JST) From: Lad Prabhakar To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar Subject: [PATCH RFC 19/30] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option Date: Wed, 20 Dec 2023 23:06:35 +0000 Message-Id: <20231220230646.219816-20-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231220230646.219816-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20231220230646.219816-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 20 Dec 2023 23:07:34 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/14155 commit 8292493c22c8e28b6e67a01e0f5c6db1cf231eb1 upstream. Add ARCH_RENESAS config option to allow selecting the Renesas RISC-V SoCs. We currently have the newly added RZ/Five (R9A07G043) RISC-V based SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley Reviewed-by: Guo Ren Acked-by: Palmer Dabbelt Link: https://lore.kernel.org/r/20221028165921.94487-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Lad Prabhakar --- arch/riscv/Kconfig.socs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 69774bb362d6..75fb0390d6bd 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -7,6 +7,11 @@ config SOC_MICROCHIP_POLARFIRE help This enables support for Microchip PolarFire SoC platforms. +config ARCH_RENESAS + bool "Renesas RISC-V SoCs" + help + This enables support for the RISC-V based Renesas SoCs. + config SOC_SIFIVE bool "SiFive SoCs" select SERIAL_SIFIVE if TTY