[6.1.y-cip,10/30] riscv: dma-mapping: only invalidate after DMA, not flush

Commit Message

Lad Prabhakar Jan. 8, 2024, 6:15 p.m. UTC

From: Arnd Bergmann <[e-mail]>

commit eb746180132a555da8cfb02d98cb6d0a9d58e870 upstream.

No other architecture intentionally writes back dirty cache lines into
a buffer that a device has just finished writing into. If the cache is
clean, this has no effect at all, but if a cacheline in the buffer has
actually been written by the CPU,  there is a driver bug that is likely
made worse by overwriting that buffer.

Signed-off-by: Arnd Bergmann <[e-mail]>
Reviewed-by: Conor Dooley <[e-mail]>
Reviewed-by: Lad Prabhakar <[e-mail]>
Acked-by: Palmer Dabbelt <[e-mail]>
Signed-off-by: Lad Prabhakar <[e-mail]>
Link: https://lore.kernel.org/r/[e-mail]
Signed-off-by: Palmer Dabbelt <[e-mail]>
Signed-off-by: Lad Prabhakar <[e-mail]>
---
 arch/riscv/mm/dma-noncoherent.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Patch

diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index d51a75864e53..94614cf61cdd 100644
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -42,7 +42,7 @@  void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
 		break;
 	case DMA_FROM_DEVICE:
 	case DMA_BIDIRECTIONAL:
-		ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
+		ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size);
 		break;
 	default:
 		break;