[6.1.y-cip,26/30] riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1}

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH 6.1.y-cip 26/30] riscv: dts: renesas: rzfive-smarc-som: Drop
 PHY interrupt support for ETH{0,1}
Date: Mon,  8 Jan 2024 18:16:08 +0000
Message-Id: <20240108181612.5651-27-prabhakar.mahadev-lad.rj@bp.renesas.com>
In-Reply-To: <20240108181612.5651-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20240108181612.5651-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
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Message ID	20240108181612.5651-27-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State	New
Headers	show Return-Path: <prabhakar.mahadev-lad.rj@bp.renesas.com> ip: 210.160.252.172, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> Cc: Biju Das <biju.das.jz@bp.renesas.com> Subject: [PATCH 6.1.y-cip 26/30] riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1} Date: Mon, 8 Jan 2024 18:16:08 +0000 Message-Id: <20240108181612.5651-27-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20240108181612.5651-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240108181612.5651-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add support for Renesas RZ/Five RISC-V SoC \| expand [6.1.y-cip,00/30] Add support for Renesas RZ/Five RISC-V SoC [6.1.y-cip,01/30] arm64: dts: renesas: rzg2ul-smarc: Drop including RZ/G2UL SoM DTSI [6.1.y-cip,02/30] arm64: dts: renesas: rzg2ul: Move PMOD_SCI0_EN macro to board DTS [6.1.y-cip,03/30] mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option dependant on ARCH_R… [6.1.y-cip,04/30] clocksource/drivers/riscv: Increase the clock source rating [6.1.y-cip,05/30] clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback [6.1.y-cip,06/30] riscv: Kconfig: Enable cpufreq kconfig menu [6.1.y-cip,07/30] dt-bindings: riscv: Sort the CPU core list alphabetically [6.1.y-cip,08/30] dt-bindings: riscv: Add Andes AX45MP core to the list [6.1.y-cip,09/30] riscv: mm: mark noncoherent_supported as __ro_after_init [6.1.y-cip,10/30] riscv: dma-mapping: only invalidate after DMA, not flush [6.1.y-cip,11/30] riscv: dma-mapping: skip invalidation before bidirectional DMA [6.1.y-cip,12/30] riscv: dma-mapping: switch over to generic implementation [6.1.y-cip,13/30] riscv: asm: vendorid_list: Add Andes Technology to the vendors list [6.1.y-cip,14/30] riscv: errata: Add Andes alternative ports [6.1.y-cip,15/30] riscv: mm: dma-noncoherent: nonstandard cache operations support [6.1.y-cip,16/30] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 c… [6.1.y-cip,17/30] cache: Add L2 cache management for Andes AX45MP RISC-V core [6.1.y-cip,18/30] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC [6.1.y-cip,19/30] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option [6.1.y-cip,20/30] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC [6.1.y-cip,21/30] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK [6.1.y-cip,22/30] riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU [6.1.y-cip,23/30] riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C [6.1.y-cip,24/30] riscv: dts: renesas: rzfive-smarc-som: Enable WDT [6.1.y-cip,25/30] riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes [6.1.y-cip,26/30] riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1} [6.1.y-cip,27/30] riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node [6.1.y-cip,28/30] riscv: dts: renesas: r9a07g043f: Add L2 cache node [6.1.y-cip,29/30] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property [6.1.y-cip,30/30] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabl…

[6.1.y-cip,26/30] riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1}

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Patch