[6.1.y-cip,04/30] clocksource/drivers/riscv: Increase the clock source rating

Commit Message

Lad Prabhakar Jan. 8, 2024, 6:15 p.m. UTC

From: Samuel Holland <[e-mail]>

commit 674402b0098b66b8ba91fe93c0d27af703256098 upstream.

RISC-V provides an architectural clock source via the time CSR. This
clock source exposes a 64-bit counter synchronized across all CPUs.
Because it is accessed using a CSR, it is much more efficient to read
than MMIO clock sources. For example, on the Allwinner D1, reading the
sun4i timer in a loop takes 131 cycles/iteration, while reading the
RISC-V time CSR takes only 5 cycles/iteration.

Adjust the RISC-V clock source rating so it is preferred over the
various platform-specific MMIO clock sources.

Signed-off-by: Samuel Holland <[e-mail]>
Acked-by: Palmer Dabbelt <[e-mail]>
Reviewed-by: Palmer Dabbelt <[e-mail]>
Reviewed-by: Anup Patel <[e-mail]>
Reviewed-by: Lad Prabhakar <[e-mail]>
Link: https://lore.kernel.org/r/[e-mail]
Signed-off-by: Daniel Lezcano <[e-mail]>
Signed-off-by: Lad Prabhakar <[e-mail]>
---
 drivers/clocksource/timer-riscv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Patch

diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index a01c2bd24134..b745db8eab93 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -73,7 +73,7 @@  static u64 notrace riscv_sched_clock(void)
 
 static struct clocksource riscv_clocksource = {
 	.name		= "riscv_clocksource",
-	.rating		= 300,
+	.rating		= 400,
 	.mask		= CLOCKSOURCE_MASK(64),
 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
 	.read		= riscv_clocksource_rdtime,