@@ -3,6 +3,9 @@ menu "Cache Drivers"
config AX45MP_L2_CACHE
bool "Andes Technology AX45MP L2 Cache controller"
+ select ARCH_HAS_SYNC_DMA_FOR_CPU
+ select ARCH_HAS_SYNC_DMA_FOR_DEVICE
+ select ARCH_HAS_SETUP_DMA_OPS
help
Support for the L2 cache controller on Andes Technology AX45MP platforms.
@@ -132,6 +132,43 @@ static void ax45mp_dma_cache_wback(phys_addr_t paddr, size_t size)
local_irq_restore(flags);
}
+void arch_sync_dma_for_device(phys_addr_t paddr,
+ size_t size, enum dma_data_direction dir)
+{
+ switch (dir) {
+ case DMA_FROM_DEVICE:
+ ax45mp_dma_cache_inv(paddr, size);
+ break;
+ case DMA_TO_DEVICE:
+ case DMA_BIDIRECTIONAL:
+ ax45mp_dma_cache_wback(paddr, size);
+ break;
+ default:
+ BUG();
+ }
+}
+
+void arch_sync_dma_for_cpu(phys_addr_t paddr,
+ size_t size, enum dma_data_direction dir)
+{
+ switch (dir) {
+ case DMA_TO_DEVICE:
+ break;
+ case DMA_FROM_DEVICE:
+ case DMA_BIDIRECTIONAL:
+ ax45mp_dma_cache_inv(paddr, size);
+ break;
+ default:
+ BUG();
+ }
+}
+
+void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
+ const struct iommu_ops *iommu, bool coherent)
+{
+ dev->dma_coherent = coherent;
+}
+
static int ax45mp_get_l2_line_size(struct device_node *np)
{
int ret;
As support for non-coherent DMA is missing in 5.10-cip for RISC-V architecture, introducing a new patch to support non-coherent DMA support on RZ/Five SoC. This enables the required config and the callbacks required to handle the non-coherent DMA support for Renesas RZ/Five SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/cache/Kconfig | 3 +++ drivers/cache/ax45mp_cache.c | 37 ++++++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+)