From patchwork Fri Feb 2 11:37:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13542787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C53BC48294 for ; Fri, 2 Feb 2024 11:38:08 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.20696.1706873879863132625 for ; Fri, 02 Feb 2024 03:38:01 -0800 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.05,238,1701097200"; d="scan'208";a="196569134" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 02 Feb 2024 20:38:00 +0900 Received: from localhost.localdomain (unknown [10.226.93.210]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id BDDAD400A0E9; Fri, 2 Feb 2024 20:37:58 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar Subject: [PATCH 6.1.y-cip 1/6] arm64: defconfig: Enable Renesas VersaClock 3 clock generator config Date: Fri, 2 Feb 2024 11:37:49 +0000 Message-Id: <20240202113754.202827-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240202113754.202827-1-biju.das.jz@bp.renesas.com> References: <20240202113754.202827-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 02 Feb 2024 11:38:08 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/14616 commit ac2453d06c768b0604e231d6effabc1c405bd802 upstream. Enable the config for the Renesas VersaClock 3 programmable clock generator, as it is populated on RZ/{G2L,G2LC} and RZ/V2L SMARC EVKs. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230824083006.88944-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 0b746403e93a..b43f74c282d3 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1055,6 +1055,7 @@ CONFIG_COMMON_CLK_CS2000_CP=y CONFIG_COMMON_CLK_FSL_SAI=y CONFIG_COMMON_CLK_S2MPS11=y CONFIG_COMMON_CLK_PWM=y +CONFIG_COMMON_CLK_VC3=y CONFIG_COMMON_CLK_VC5=y CONFIG_COMMON_CLK_BD718XX=m CONFIG_CLK_RASPBERRYPI=m