[5.10.y-cip,28/48] dt-bindings: riscv: Sort the CPU core list alphabetically

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH 5.10.y-cip 28/48] dt-bindings: riscv: Sort the CPU core list
 alphabetically
Date: Mon,  5 Feb 2024 12:41:15 +0000
Message-Id: <20240205124135.14779-29-prabhakar.mahadev-lad.rj@bp.renesas.com>
In-Reply-To: <20240205124135.14779-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20240205124135.14779-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
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Message ID	20240205124135.14779-29-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State	New
Headers	show Return-Path: <prabhakar.mahadev-lad.rj@bp.renesas.com> ip: 210.160.252.172, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> Cc: Biju Das <biju.das.jz@bp.renesas.com> Subject: [PATCH 5.10.y-cip 28/48] dt-bindings: riscv: Sort the CPU core list alphabetically Date: Mon, 5 Feb 2024 12:41:15 +0000 Message-Id: <20240205124135.14779-29-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20240205124135.14779-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240205124135.14779-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add support for Renesas RZ/Five RISC-V SoC \| expand [5.10.y-cip,00/48] Add support for Renesas RZ/Five RISC-V SoC [5.10.y-cip,01/48] ASoC: dt-bindings: renesas,rz-ssi: Update interrupts and interrupt-names propert… [5.10.y-cip,02/48] ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels [5.10.y-cip,03/48] arm64: dts: renesas: r9a07g054: Update IRQ numbers for SSI channels [5.10.y-cip,04/48] arm64: dts: renesas: r9a07g044: Update IRQ numbers for SSI channels [5.10.y-cip,05/48] arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to board DTS [5.10.y-cip,06/48] arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into board DTS [5.10.y-cip,07/48] arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify … [5.10.y-cip,08/48] arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels [5.10.y-cip,09/48] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts [5.10.y-cip,10/48] cacheinfo: clear cache_leaves(cpu) in free_cache_attributes() [5.10.y-cip,11/48] riscv: Kconfig: Enable cpufreq kconfig menu [5.10.y-cip,12/48] dma-direct: add support for dma_coherent_default_memory [5.10.y-cip,13/48] dma-mapping: allow using the global coherent pool for !ARM [5.10.y-cip,14/48] dma-mapping: simplify dma_init_coherent_memory [5.10.y-cip,15/48] dma-mapping: add a dma_init_global_coherent helper [5.10.y-cip,16/48] dma-mapping: make the global coherent pool conditional [5.10.y-cip,17/48] of: also handle dma-noncoherent in of_dma_is_coherent() [5.10.y-cip,18/48] of/irq: Use interrupts-extended to find parent [5.10.y-cip,19/48] irqchip/sifive-plic: Improve naming scheme for per context offsets [5.10.y-cip,20/48] irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode [5.10.y-cip,21/48] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC [5.10.y-cip,22/48] irqchip/sifive-plic: Make better use of the effective affinity mask [5.10.y-cip,23/48] irqchip/sifive-plic: Separate the enable and mask operations [5.10.y-cip,24/48] clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC [5.10.y-cip,25/48] clocksource/drivers/riscv: Increase the clock source rating [5.10.y-cip,26/48] clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback [5.10.y-cip,27/48] mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option dependant on ARCH_… [5.10.y-cip,28/48] dt-bindings: riscv: Sort the CPU core list alphabetically [5.10.y-cip,29/48] dt-bindings: riscv: Add Andes AX45MP core to the list [5.10.y-cip,30/48] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Defin… [5.10.y-cip,31/48] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 … [5.10.y-cip,32/48] soc: renesas: Identify RZ/Five SoC [5.10.y-cip,33/48] clk: renesas: r9a07g043: Add support for RZ/Five SoC [5.10.y-cip,34/48] cache: Add L2 cache management for Andes AX45MP RISC-V core [5.10.y-cip,35/48] cache: ax45mp_cache: Add non coherent support [5.10.y-cip,36/48] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC [5.10.y-cip,37/48] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option [5.10.y-cip,38/48] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC [5.10.y-cip,39/48] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK [5.10.y-cip,40/48] riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/T… [5.10.y-cip,41/48] riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C [5.10.y-cip,42/48] riscv: dts: renesas: rzfive-smarc-som: Enable WDT [5.10.y-cip,43/48] riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes [5.10.y-cip,44/48] riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1} [5.10.y-cip,45/48] riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node [5.10.y-cip,46/48] riscv: dts: renesas: r9a07g043f: Add L2 cache node [5.10.y-cip,47/48] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property [5.10.y-cip,48/48] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disab…

[5.10.y-cip,28/48] dt-bindings: riscv: Sort the CPU core list alphabetically

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