From patchwork Tue Feb 6 12:27:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 13547183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0657FC4829A for ; Tue, 6 Feb 2024 12:28:36 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web11.20171.1707222496328553437 for ; Tue, 06 Feb 2024 04:28:26 -0800 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.05,247,1701097200"; d="scan'208";a="193048762" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 06 Feb 2024 21:28:25 +0900 Received: from Ubuntu-22.. (unknown [10.226.93.78]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 8BCFF4005E16; Tue, 6 Feb 2024 21:28:24 +0900 (JST) From: Lad Prabhakar To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das Subject: [PATCH v2 5.10.y-cip 24/44] dt-bindings: riscv: Sort the CPU core list alphabetically Date: Tue, 6 Feb 2024 12:27:14 +0000 Message-Id: <20240206122734.13477-25-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240206122734.13477-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240206122734.13477-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 06 Feb 2024 12:28:36 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/14808 commit 57e1b873c2f54253f4c81bddb782e183ee6544ae upstream. Sort the CPU cores list alphabetically for maintenance. Signed-off-by: Lad Prabhakar Reviewed-by: Krzysztof Kozlowski Reviewed-by: Heiko Stuebner Reviewed-by: Conor Dooley Reviewed-by: Guo Ren Acked-by: Palmer Dabbelt Link: https://lore.kernel.org/r/20221028165921.94487-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [PL: dropped unsupported SoCs] Signed-off-by: Lad Prabhakar Reviewed-by: Nobuhiro Iwamatsu --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c6925e0b16e46..cd218c8e21042 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -27,12 +27,12 @@ properties: oneOf: - items: - enum: - - sifive,rocket0 - sifive,e5 - sifive,e51 - - sifive,u54-mc - - sifive,u54 + - sifive,rocket0 - sifive,u5 + - sifive,u54 + - sifive,u54-mc - const: riscv - const: riscv # Simulator only description: