[6.1.y-cip,40/44] arm64: dts: renesas: r9a08g045: Add missing cache-level for L3 cache

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

From: Claudiu <claudiu.beznea@tuxon.dev>
To: nobuhiro1.iwamatsu@toshiba.co.jp,
	pavel@denx.de
Cc: cip-dev@lists.cip-project.org,
	biju.das.jz@bp.renesas.com,
	prabhakar.mahadev-lad.rj@bp.renesas.com
Subject: [PATCH 6.1.y-cip 40/44] arm64: dts: renesas: r9a08g045: Add missing
 cache-level for L3 cache
Date: Fri, 19 Apr 2024 14:38:38 +0300
Message-Id: <20240419113842.3675543-41-claudiu.beznea.uj@bp.renesas.com>
In-Reply-To: <20240419113842.3675543-1-claudiu.beznea.uj@bp.renesas.com>
References: <20240419113842.3675543-1-claudiu.beznea.uj@bp.renesas.com>
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Message ID	20240419113842.3675543-41-claudiu.beznea.uj@bp.renesas.com (mailing list archive)
State	New
Headers	show Return-Path: <claudiu.beznea@tuxon.dev> ip: 209.85.167.46, mailfrom: claudiu.beznea@tuxon.dev) From: Claudiu <claudiu.beznea@tuxon.dev> To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Subject: [PATCH 6.1.y-cip 40/44] arm64: dts: renesas: r9a08g045: Add missing cache-level for L3 cache Date: Fri, 19 Apr 2024 14:38:38 +0300 Message-Id: <20240419113842.3675543-41-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: <20240419113842.3675543-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419113842.3675543-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add initial support for the Renesas RZ/G3S SoC \| expand [6.1.y-cip,00/44] Add initial support for the Renesas RZ/G3S SoC [6.1.y-cip,01/44] dt-bindings: soc: renesas: renesas,rzg2l-sysc: Document RZ/G3S SoC [6.1.y-cip,02/44] dt-bindings: soc: renesas: Document Renesas RZ/G3S SoC variants [6.1.y-cip,03/44] clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM [6.1.y-cip,04/44] clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic() [6.1.y-cip,05/44] clk: renesas: rzg2l: Use u32 for flag and mux_flags [6.1.y-cip,06/44] clk: renesas: rzg2l: Simplify .determine_rate() [6.1.y-cip,07/44] clk: renesas: rzg2l: Use core->name for clock name [6.1.y-cip,08/44] clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable() [6.1.y-cip,09/44] clk: renesas: rzg2l: Remove critical area [6.1.y-cip,10/44] clk: renesas: rzg2l: Add support for RZ/G3S PLL [6.1.y-cip,11/44] clk: renesas: rzg2l: Add struct clk_hw_data [6.1.y-cip,12/44] clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header [6.1.y-cip,13/44] clk: renesas: rzg2l: Refactor SD mux driver [6.1.y-cip,14/44] clk: renesas: rzg2l: Add divider clock for RZ/G3S [6.1.y-cip,15/44] dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoC [6.1.y-cip,16/44] clk: renesas: Add minimal boot support for RZ/G3S SoC [6.1.y-cip,17/44] clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2 [6.1.y-cip,18/44] clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 mux [6.1.y-cip,19/44] soc: renesas: Use "#ifdef" for single-symbol definition checks [6.1.y-cip,20/44] soc: renesas: Identify RZ/G3S SoC [6.1.y-cip,21/44] pinctrl: renesas: rzg2l: Make struct rzg2l_pinctrl_data::dedicated_pins constant [6.1.y-cip,22/44] pinctrl: renesas: rzg2l: Rename rzg2l_gpio_configs[] [6.1.y-cip,23/44] pinctrl: renesas: rzg2l: Add validation of GPIO pin in rzg2l_gpio_request() [6.1.y-cip,24/44] pinctrl: renesas: rzg2l: Index all registers based on port offset [6.1.y-cip,25/44] pinctrl: renesas: rzg2l: Adapt for different SD/PWPR register offsets [6.1.y-cip,26/44] pinctrl: renesas: rzg2l: Adapt function number for RZ/G3S [6.1.y-cip,27/44] pinctrl: renesas: rzg2l: Move DS and OI to SoC-specific configuration [6.1.y-cip,28/44] pinctrl: renesas: rzg2l: Add support for different DS values on different groups [6.1.y-cip,29/44] dt-bindings: pinctrl: renesas: Document RZ/G3S SoC [6.1.y-cip,30/44] pinctrl: renesas: rzg2l: Add RZ/G3S support [6.1.y-cip,31/44] dt-bindings: mmc: renesas,sdhi: Document RZ/G3S support [6.1.y-cip,32/44] dt-bindings: serial: renesas,scif: document r9a08g045 support [6.1.y-cip,33/44] dt-bindings: soc: renesas: Document RZ/G3S SMARC SoM [6.1.y-cip,34/44] dt-bindings: soc: renesas: Document SMARC Carrier-II EVK [6.1.y-cip,35/44] arm64: dts: renesas: Add initial DTSI for RZ/G3S SoC [6.1.y-cip,36/44] arm64: dts: renesas: Add initial support for RZ/G3S SMARC SoM [6.1.y-cip,37/44] arm64: dts: renesas: Add initial device tree for RZ SMARC Carrier-II Board [6.1.y-cip,38/44] arm64: dts: renesas: Add initial device tree for RZ/G3S SMARC EVK board [6.1.y-cip,39/44] arm64: dts: renesas: r9a08g045: Add nodes for SDHI1 and SDHI2 [6.1.y-cip,40/44] arm64: dts: renesas: r9a08g045: Add missing cache-level for L3 cache [6.1.y-cip,41/44] arm64: dts: renesas: rzg3s-smarc-som: Spelling s/device-type/device_type/ [6.1.y-cip,42/44] arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2 [6.1.y-cip,43/44] arm64: dts: renesas: rzg3s-smarc: Enable SDHI1 [6.1.y-cip,44/44] arm64: defconfig: Enable RZ/G3S (R9A08G045) SoC

[6.1.y-cip,40/44] arm64: dts: renesas: r9a08g045: Add missing cache-level for L3 cache

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Patch