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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:55 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 45/47] arm64: dts: renesas: rzg3s-smarc-som: Use switches' names to select on-board functionalities Date: Wed, 29 May 2024 11:10:37 +0300 Message-Id: <20240529081039.639010-46-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:12:07 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16025 From: Claudiu Beznea commit 447765986dbfc321e37b13d7c276b106a469ec0b upstream. The intention of the SW_SD0_DEV_SEL and SW_SD2_EN macros was to reflect the state of the SW_CONFIG individual switches available on the RZ/G3S Smarc Module, and at the same time to have a descriptive name for the switches themselves. Each individual switch is associated with a signal name, which might be active-low or not on the board. Using signal names instead of SW_CONFIG switch names may be confusing for a user who just playes with switches to select individual functionalities, but also for an advanced user who looks at the schematics. To avoid even further confusion, use the switches' names here and instantiate them with an ON/OFF state. This should be simpler, even though the name of the switches is not that intuitive. The switches' names documentation reflects the switches' purposes. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-11-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 34 ++++++++++++------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 01a4a9da7afc..f59094701a4a 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -9,23 +9,31 @@ #include /* - * Signals of SW_CONFIG switches: - * @SW_SD0_DEV_SEL: - * 0 - SD0 is connected to eMMC - * 1 - SD0 is connected to uSD0 card - * @SW_SD2_EN: - * 0 - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC - * 1 - SD2 is connected to SoC + * On-board switches' states: + * @SW_OFF: switch's state is OFF + * @SW_ON: switch's state is ON */ -#define SW_SD0_DEV_SEL 1 -#define SW_SD2_EN 1 +#define SW_OFF 0 +#define SW_ON 1 + +/* + * SW_CONFIG[x] switches' states: + * @SW_CONFIG2: + * SW_OFF - SD0 is connected to eMMC + * SW_ON - SD0 is connected to uSD0 card + * @SW_CONFIG3: + * SW_OFF - SD2 is connected to SoC + * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC + */ +#define SW_CONFIG2 SW_ON +#define SW_CONFIG3 SW_OFF / { compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; aliases { mmc0 = &sdhi0; -#if SW_SD2_EN +#if SW_CONFIG3 == SW_OFF mmc2 = &sdhi2; #endif }; @@ -50,7 +58,7 @@ vcc_sdhi0: regulator0 { enable-active-high; }; -#if SW_SD0_DEV_SEL +#if SW_CONFIG2 == SW_ON vccq_sdhi0: regulator1 { compatible = "regulator-gpio"; regulator-name = "SDHI0 VccQ"; @@ -85,7 +93,7 @@ &extal_clk { clock-frequency = <24000000>; }; -#if SW_SD0_DEV_SEL +#if SW_CONFIG2 == SW_ON /* SD0 slot */ &sdhi0 { pinctrl-0 = <&sdhi0_pins>; @@ -116,7 +124,7 @@ &sdhi0 { }; #endif -#if SW_SD2_EN +#if SW_CONFIG3 == SW_OFF &sdhi2 { pinctrl-0 = <&sdhi2_pins>; pinctrl-names = "default";