diff mbox series

[5.10.y-cip,08/19] pinctrl: renesas: rzg2l: Avoid configuring ISEL in gpio_irq_{en,dis}able*(

Message ID 20240607140711.2497286-9-claudiu.beznea.uj@bp.renesas.com (mailing list archive)
State New
Headers show
Series Add suspend to RAM support for pin and IA55 IRQ controllers | expand

Commit Message

Claudiu Beznea June 7, 2024, 2:07 p.m. UTC 
From: Biju Das <biju.das.jz@bp.renesas.com>

commit 1d2da79708cb4e23ec3d19c6c5b528753ca08e67 upstream.

Currently on irq_disable(), we are disabling gpio interrupt enable(ISEL).
That means the pin is just gpio input and not gpio input interrupt any
more.  So, move configuring ISEL in rzg2l_gpio_child_to_parent_hwirq()/
rzg2l_gpio_irq_domain_free() so that the pin will be gpioint always even
during irq_disable().

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240206135318.165426-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 40b0c325f509..5f0ed9a9a44a 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -1832,22 +1832,18 @@  static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl,
 static void rzg2l_gpio_irq_disable(struct irq_data *d)
 {
 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
-	struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
 	unsigned int hwirq = irqd_to_hwirq(d);
 
 	irq_chip_disable_parent(d);
-	rzg2l_gpio_irq_endisable(pctrl, hwirq, false);
 	gpiochip_disable_irq(gc, hwirq);
 }
 
 static void rzg2l_gpio_irq_enable(struct irq_data *d)
 {
 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
-	struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
 	unsigned int hwirq = irqd_to_hwirq(d);
 
 	gpiochip_enable_irq(gc, hwirq);
-	rzg2l_gpio_irq_endisable(pctrl, hwirq, true);
 	irq_chip_enable_parent(d);
 }
 
@@ -1927,6 +1923,7 @@  static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
 		goto err;
 	}
 
+	rzg2l_gpio_irq_endisable(pctrl, child, true);
 	pctrl->hwirq[irq] = child;
 	irq += RZG2L_TINT_IRQ_START_INDEX;
 
@@ -1973,6 +1970,7 @@  static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int v
 
 		for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) {
 			if (pctrl->hwirq[i] == hwirq) {
+				rzg2l_gpio_irq_endisable(pctrl, hwirq, false);
 				rzg2l_gpio_free(gc, hwirq);
 				spin_lock_irqsave(&pctrl->bitmap_lock, flags);
 				bitmap_release_region(pctrl->tint_slot, i, get_order(1));