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([82.78.167.189]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581870sm251987466b.25.2024.06.07.07.09.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jun 2024 07:09:09 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Subject: [PATCH 6.1.y-cip 08/17] pinctrl: renesas: rzg2l: Avoid configuring ISEL in gpio_irq_{en,dis}able*( Date: Fri, 7 Jun 2024 17:08:47 +0300 Message-Id: <20240607140856.2497508-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> References: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 07 Jun 2024 14:09:21 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16169 From: Biju Das commit 1d2da79708cb4e23ec3d19c6c5b528753ca08e67 upstream. Currently on irq_disable(), we are disabling gpio interrupt enable(ISEL). That means the pin is just gpio input and not gpio input interrupt any more. So, move configuring ISEL in rzg2l_gpio_child_to_parent_hwirq()/ rzg2l_gpio_irq_domain_free() so that the pin will be gpioint always even during irq_disable(). Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240206135318.165426-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 514aebc3fc8e..38cff01a5852 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1835,22 +1835,18 @@ static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, static void rzg2l_gpio_irq_disable(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); unsigned int hwirq = irqd_to_hwirq(d); irq_chip_disable_parent(d); - rzg2l_gpio_irq_endisable(pctrl, hwirq, false); gpiochip_disable_irq(gc, hwirq); } static void rzg2l_gpio_irq_enable(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); unsigned int hwirq = irqd_to_hwirq(d); gpiochip_enable_irq(gc, hwirq); - rzg2l_gpio_irq_endisable(pctrl, hwirq, true); irq_chip_enable_parent(d); } @@ -1932,6 +1928,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, goto err; } + rzg2l_gpio_irq_endisable(pctrl, child, true); pctrl->hwirq[irq] = child; irq += RZG2L_TINT_IRQ_START_INDEX; @@ -1975,6 +1972,7 @@ static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int v for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { if (pctrl->hwirq[i] == hwirq) { + rzg2l_gpio_irq_endisable(pctrl, hwirq, false); rzg2l_gpio_free(gc, hwirq); spin_lock_irqsave(&pctrl->bitmap_lock, flags); bitmap_release_region(pctrl->tint_slot, i, get_order(1));