From patchwork Mon Oct 28 20:03:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 13854015 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E5A1D3E2D6 for ; Mon, 28 Oct 2024 20:04:45 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web10.2554.1730145876235235871 for ; Mon, 28 Oct 2024 13:04:36 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.11,239,1725289200"; d="scan'208";a="227219310" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 29 Oct 2024 05:04:35 +0900 Received: from Ubuntu-22.. (unknown [10.226.93.179]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id C87EC408CD26; Tue, 29 Oct 2024 05:04:26 +0900 (JST) From: Lad Prabhakar To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das Subject: [PATCH 5.10.y-cip 19/27] media: platform: rzg2l-cru: rzg2l-ip: Add delay after D-PHY reset Date: Mon, 28 Oct 2024 20:03:41 +0000 Message-ID: <20241028200349.9620-20-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241028200349.9620-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241028200349.9620-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Mon, 28 Oct 2024 20:04:45 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17102 From: Biju Das commit 9c7fa014ca320b0eb95062922a73563aa9734cd0 upstream. As per section 35.3.1 Starting Reception for the MIPI CSI-2 Input on the latest hardware manual (R01UH0914EJ0140 Rev.1.40) it is mentioned that after DPHY reset, we need to wait for 1 msec or more before start receiving data from the sensor. So add a delay after pre_streamon(). Signed-off-by: Biju Das Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20240213181233.242316-3-biju.das.jz@bp.renesas.com Signed-off-by: Laurent Pinchart Signed-off-by: Hans Verkuil Signed-off-by: Lad Prabhakar --- drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c index 3a9f282a87bbb..fc1270f849cb0 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c @@ -5,6 +5,7 @@ * Copyright (C) 2022 Renesas Electronics Corp. */ +#include #include "rzg2l-cru.h" struct rzg2l_cru_ip_format { @@ -70,6 +71,8 @@ static int rzg2l_cru_ip_s_stream(struct v4l2_subdev *sd, int enable) if (ret) return ret; + fsleep(1000); + ret = rzg2l_cru_start_image_processing(cru); if (ret) { v4l2_subdev_call(cru->ip.remote, video, post_streamoff);