From patchwork Fri Nov 1 12:57:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 13859337 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F138E6B275 for ; Fri, 1 Nov 2024 12:58:55 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web11.36928.1730465925329956404 for ; Fri, 01 Nov 2024 05:58:46 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.11,249,1725289200"; d="scan'208";a="223655357" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 01 Nov 2024 21:58:44 +0900 Received: from Ubuntu-22.. (unknown [10.226.92.182]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id D04CF4006DF6; Fri, 1 Nov 2024 21:58:39 +0900 (JST) From: Lad Prabhakar To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das Subject: [PATCH v2 5.10.y-cip 27/28] arm64: dts: renesas: rzg2l-smarc: Enable CRU, CSI support Date: Fri, 1 Nov 2024 12:57:45 +0000 Message-ID: <20241101125746.33222-28-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241101125746.33222-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241101125746.33222-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 01 Nov 2024 12:58:55 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17162 commit 3d52973db7457362e54b5b62242671eee80b2c14 upstream. Enable CRU, CSI on RZ/G2L SMARC EVK and tie the CSI to OV5645 sensor using Device Tree overlay. rz-smarc-cru-csi-ov5645.dtsi is created so that RZ/G2L alike EVKs can make use of it. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230322125648.24948-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [PL: dropped overlay support and enabled directly in board dts] Signed-off-by: Lad Prabhakar --- .../dts/renesas/rz-smarc-cru-csi-ov5645.dtsi | 80 +++++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 8 ++ 2 files changed, 88 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi new file mode 100644 index 0000000000000..c5bb63c63b470 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common Device Tree for the RZ/G2L SMARC EVK (and alike EVKs) with + * OV5645 camera connected to CSI and CRU enabled. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +&{/} { + ov5645_vdddo_1v8: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "camera_vdddo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ov5645_vdda_2v8: 2p8v { + compatible = "regulator-fixed"; + regulator-name = "camera_vdda"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ov5645_vddd_1v5: 1p5v { + compatible = "regulator-fixed"; + regulator-name = "camera_vddd"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + ov5645_fixed_clk: osc25250-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&cru { + status = "okay"; +}; + +&csi2 { + status = "okay"; + + ports { + port@0 { + csi2_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&ov5645_ep>; + }; + }; + }; +}; + +&OV5645_PARENT_I2C { + #address-cells = <1>; + #size-cells = <0>; + + ov5645: camera@3c { + compatible = "ovti,ov5645"; + reg = <0x3c>; + clocks = <&ov5645_fixed_clk>; + clock-frequency = <24000000>; + vdddo-supply = <&ov5645_vdddo_1v8>; + vdda-supply = <&ov5645_vdda_2v8>; + vddd-supply = <&ov5645_vddd_1v5>; + + port { + ov5645_ep: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&csi2_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index ee3d96fdb6168..90ae3259fd825 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -8,6 +8,9 @@ #include #include +#define OV5645_PARENT_I2C i2c0 +#include "rz-smarc-cru-csi-ov5645.dtsi" + / { aliases { serial1 = &scif2; @@ -159,6 +162,11 @@ &spi1 { }; #endif /* PMOD_MTU3 */ +&ov5645 { + enable-gpios = <&pinctrl RZG2L_GPIO(2, 0) GPIO_ACTIVE_HIGH>; + reset-gpios = <&pinctrl RZG2L_GPIO(40, 2) GPIO_ACTIVE_LOW>; +}; + /* * To enable SCIF2 (SER0) on PMOD1 (CN7) * SW1 should be at position 2->3 so that SER0_CTS# line is activated