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Mon, 31 Mar 2025 10:46:16 +0000 From: Tommaso Merciai To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek CC: Biju Das , Lad Prabhakar , tomm.merciai@gmail.com Subject: [PATCH 6.1.y-cip 15/43] pinctrl: renesas: rzg2l: Add support for pull-up/down Date: Mon, 31 Mar 2025 12:44:46 +0200 Message-ID: <20250331104514.79090-16-tommaso.merciai.xr@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250331104514.79090-1-tommaso.merciai.xr@bp.renesas.com> References: <20250331104514.79090-1-tommaso.merciai.xr@bp.renesas.com> X-ClientProxiedBy: FR4P281CA0148.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:b8::13) To OS9PR01MB13950.jpnprd01.prod.outlook.com (2603:1096:604:35e::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OS9PR01MB13950:EE_|TYCPR01MB9796:EE_ X-MS-Office365-Filtering-Correlation-Id: 8161ae78-f8f7-4fed-a1e2-08dd70414354 X-LD-Processed: 53d82571-da19-47e4-9cb4-625a166a4a2a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|52116014|376014|38350700014; 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Mon, 31 Mar 2025 10:46:21 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/18403 From: Lad Prabhakar commit 19d4bce9ce876ad0ee4240ebd849b730b3dc3763 upstream. Add support to configure bias-disable, bias-pull-up, and bias-pull-down properties of the pin. Two new function pointers, hw_to_bias_param() and bias_param_to_hw(), are introduced in the struct rzg2l_pinctrl_data to configure bias settings, as the values in the PUPD register differ when compared to the RZ/G2L family and the RZ/V2H(P) SoC. Value | RZ/G2L | RZ/V2H --------------------------------- 00b: | Bias Disabled | Pull up/down disabled 01b: | Pull-up | Pull up/down disabled 10b: | Pull-down | Pull-down 11b: | Prohibited | Pull-up Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240530173857.164073-12-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Tommaso Merciai --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 72 +++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 596e101f5b2d4..33c96661092bf 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -128,6 +128,7 @@ #define IOLH(off) (0x1000 + (off) * 8) #define SR(off) (0x1400 + (off) * 8) #define IEN(off) (0x1800 + (off) * 8) +#define PUPD(off) (0x1C00 + (off) * 8) #define ISEL(off) (0x2C00 + (off) * 8) #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) @@ -146,6 +147,7 @@ #define IEN_MASK 0x01 #define IOLH_MASK 0x03 #define SR_MASK 0x01 +#define PUPD_MASK 0x03 #define PM_INPUT 0x1 #define PM_OUTPUT 0x2 @@ -258,6 +260,8 @@ struct rzg2l_pinctrl_data { void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset); u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin); int (*oen_write)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen); + int (*hw_to_bias_param)(unsigned int val); + int (*bias_param_to_hw)(enum pin_config_param param); }; /** @@ -1000,6 +1004,38 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 return 0; } +static int rzg2l_hw_to_bias_param(unsigned int bias) +{ + switch (bias) { + case 0: + return PIN_CONFIG_BIAS_DISABLE; + case 1: + return PIN_CONFIG_BIAS_PULL_UP; + case 2: + return PIN_CONFIG_BIAS_PULL_DOWN; + default: + break; + } + + return -EINVAL; +} + +static int rzg2l_bias_param_to_hw(enum pin_config_param param) +{ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + return 0; + case PIN_CONFIG_BIAS_PULL_UP: + return 1; + case PIN_CONFIG_BIAS_PULL_DOWN: + return 2; + default: + break; + } + + return -EINVAL; +} + static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, unsigned int _pin, unsigned long *config) @@ -1058,6 +1094,23 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, arg = rzg2l_read_pin_config(pctrl, SR(off), bit, SR_MASK); break; + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + if (!(cfg & PIN_CFG_PUPD)) + return -EINVAL; + + arg = rzg2l_read_pin_config(pctrl, PUPD(off), bit, PUPD_MASK); + ret = pctrl->data->hw_to_bias_param(arg); + if (ret < 0) + return ret; + + if (ret != param) + return -EINVAL; + /* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */ + arg = 1; + break; + case PIN_CONFIG_DRIVE_STRENGTH: { unsigned int index; @@ -1173,6 +1226,19 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, rzg2l_rmw_pin_config(pctrl, SR(off), bit, SR_MASK, arg); break; + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + if (!(cfg & PIN_CFG_PUPD)) + return -EINVAL; + + ret = pctrl->data->bias_param_to_hw(param); + if (ret < 0) + return ret; + + rzg2l_rmw_pin_config(pctrl, PUPD(off), bit, PUPD_MASK, ret); + break; + case PIN_CONFIG_DRIVE_STRENGTH: arg = pinconf_to_config_argument(_configs[i]); @@ -2645,6 +2711,8 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { .pmc_writeb = &rzg2l_pmc_writeb, .oen_read = &rzg2l_read_oen, .oen_write = &rzg2l_write_oen, + .hw_to_bias_param = &rzg2l_hw_to_bias_param, + .bias_param_to_hw = &rzg2l_bias_param_to_hw, }; static struct rzg2l_pinctrl_data r9a07g044_data = { @@ -2660,6 +2728,8 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { .pmc_writeb = &rzg2l_pmc_writeb, .oen_read = &rzg2l_read_oen, .oen_write = &rzg2l_write_oen, + .hw_to_bias_param = &rzg2l_hw_to_bias_param, + .bias_param_to_hw = &rzg2l_bias_param_to_hw, }; static struct rzg2l_pinctrl_data r9a08g045_data = { @@ -2674,6 +2744,8 @@ static struct rzg2l_pinctrl_data r9a08g045_data = { .pmc_writeb = &rzg2l_pmc_writeb, .oen_read = &rzg2l_read_oen, .oen_write = &rzg2l_write_oen, + .hw_to_bias_param = &rzg2l_hw_to_bias_param, + .bias_param_to_hw = &rzg2l_bias_param_to_hw, }; static const struct of_device_id rzg2l_pinctrl_of_table[] = {