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Mon, 31 Mar 2025 10:46:31 +0000 From: Tommaso Merciai To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek CC: Biju Das , Lad Prabhakar , tomm.merciai@gmail.com Subject: [PATCH 6.1.y-cip 20/43] pinctrl: renesas: rzg2l: Update PIN_CFG_MASK() macro to be 32-bit wide Date: Mon, 31 Mar 2025 12:44:51 +0200 Message-ID: <20250331104514.79090-21-tommaso.merciai.xr@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250331104514.79090-1-tommaso.merciai.xr@bp.renesas.com> References: <20250331104514.79090-1-tommaso.merciai.xr@bp.renesas.com> X-ClientProxiedBy: FR4P281CA0148.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:b8::13) To OS9PR01MB13950.jpnprd01.prod.outlook.com (2603:1096:604:35e::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OS9PR01MB13950:EE_|TYWPR01MB10032:EE_ X-MS-Office365-Filtering-Correlation-Id: b2b3391b-7149-4d3b-88b3-08dd70414c3c X-LD-Processed: 53d82571-da19-47e4-9cb4-625a166a4a2a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|52116014|376014|38350700014; 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Mon, 31 Mar 2025 10:46:41 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/18408 From: Lad Prabhakar commit 0a5e40f9c29756dec3da573edce3f4b3194e6f91 upstream. Modify the `PIN_CFG_MASK()` macro to be 32-bit wide. The current maximum value for `PIN_CFG_*` is `BIT(21)`, which fits within a 32-bit mask. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Tested-by: Claudiu Beznea Link: https://lore.kernel.org/r/20240618174831.415583-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Tommaso Merciai --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 8c29c8d3c5743..b4ad4a4d20463 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -88,7 +88,7 @@ #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(62, 55) #define PIN_CFG_PIN_REG_MASK GENMASK_ULL(54, 47) -#define PIN_CFG_MASK GENMASK_ULL(46, 0) +#define PIN_CFG_MASK GENMASK_ULL(31, 0) /* * m indicates the bitmap of supported pins, a is the register index @@ -1187,7 +1187,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, u64 *pin_data = pin->drv_data; unsigned int arg = 0; u32 off; - u64 cfg; + u32 cfg; int ret; u8 bit; @@ -1322,7 +1322,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, u64 *pin_data = pin->drv_data; unsigned int i, arg, index; u32 off, param; - u64 cfg; + u32 cfg; int ret; u8 bit; @@ -2755,9 +2755,9 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen for (u32 port = 0; port < nports; port++) { bool has_iolh, has_ien; - u64 cfg, caps; + u32 off, caps; u8 pincnt; - u32 off; + u64 cfg; cfg = pctrl->data->port_pin_configs[port]; off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); @@ -2801,7 +2801,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend) { struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache; - u64 caps; + u32 caps; u32 i; /*