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Mon, 31 Mar 2025 10:47:34 +0000 From: Tommaso Merciai To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek CC: Biju Das , Lad Prabhakar , tomm.merciai@gmail.com Subject: [PATCH 6.1.y-cip 41/43] pinctrl: renesas: rzg2l: Fix PFC_MASK for RZ/V2H and RZ/G3E Date: Mon, 31 Mar 2025 12:45:12 +0200 Message-ID: <20250331104514.79090-42-tommaso.merciai.xr@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250331104514.79090-1-tommaso.merciai.xr@bp.renesas.com> References: <20250331104514.79090-1-tommaso.merciai.xr@bp.renesas.com> X-ClientProxiedBy: FR4P281CA0148.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:b8::13) To OS9PR01MB13950.jpnprd01.prod.outlook.com (2603:1096:604:35e::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OS9PR01MB13950:EE_|OSCPR01MB13299:EE_ X-MS-Office365-Filtering-Correlation-Id: 179182d7-da0d-4f11-b237-08dd704171ee X-LD-Processed: 53d82571-da19-47e4-9cb4-625a166a4a2a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|52116014|376014|1800799024|38350700014; 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Mon, 31 Mar 2025 10:47:41 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/18429 From: Lad Prabhakar commit accabfaae0940f9427c782bfee7340ce4c15151c upstream. The PFC_MASK value for the PFC_mx registers is currently hardcoded to 0x07, which is correct for SoCs in the RZ/G2L family, but insufficient for RZ/V2H and RZ/G3E, where the mask value should be 0x0f. This discrepancy causes incorrect PFC register configuration on RZ/V2H and RZ/G3E SoCs. On RZ/G2L, the PFC_mx bitfields are also 4 bits wide, with bit 4 marked as reserved. The reserved bits are documented to read as zero and be ignored when written. Updating the PFC_MASK definition from 0x07 to 0x0f ensures compatibility with both SoC families while maintaining correct behavior on RZ/G2L. Fixes: 9bd95ac86e70 ("pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC") Cc: stable@vger.kernel.org Reported-by: Hien Huynh Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250110221045.594596-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Tommaso Merciai --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 36ef1b558ae34..6e57153286828 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -158,7 +158,7 @@ #define PWPR_REGWE_B BIT(5) /* OEN Register Write Enable, known only in RZ/V2H(P) */ #define PM_MASK 0x03 -#define PFC_MASK 0x07 +#define PFC_MASK 0x0f #define IEN_MASK 0x01 #define IOLH_MASK 0x03 #define SR_MASK 0x01