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Mon, 31 Mar 2025 10:47:37 +0000 From: Tommaso Merciai To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek CC: Biju Das , Lad Prabhakar , tomm.merciai@gmail.com Subject: [PATCH 6.1.y-cip 42/43] arm64: dts: renesas: r9a09g047: Add pincontrol node Date: Mon, 31 Mar 2025 12:45:13 +0200 Message-ID: <20250331104514.79090-43-tommaso.merciai.xr@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250331104514.79090-1-tommaso.merciai.xr@bp.renesas.com> References: <20250331104514.79090-1-tommaso.merciai.xr@bp.renesas.com> X-ClientProxiedBy: FR4P281CA0148.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:b8::13) To OS9PR01MB13950.jpnprd01.prod.outlook.com (2603:1096:604:35e::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OS9PR01MB13950:EE_|OSCPR01MB13299:EE_ X-MS-Office365-Filtering-Correlation-Id: a9c41809-9a35-48f9-4309-08dd70417399 X-LD-Processed: 53d82571-da19-47e4-9cb4-625a166a4a2a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|52116014|376014|1800799024|38350700014; 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Mon, 31 Mar 2025 10:47:41 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/18430 From: Biju Das commit 987040d4601e98e32c53837ef76aad115c4966f7 upstream. Add pincontrol node to RZ/G3E ("R9A09G047") SoC DTSI. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das Link: https://lore.kernel.org/20241216195325.164212-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Tommaso Merciai --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 39a7cfb3095b0..15711f9b6038c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -131,6 +131,19 @@ soc: soc { #size-cells = <2>; ranges; + pinctrl: pinctrl@10410000 { + compatible = "renesas,r9a09g047-pinctrl"; + reg = <0 0x10410000 0 0x10000>; + clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 232>; + #interrupt-cells = <2>; + interrupt-controller; + power-domains = <&cpg>; + resets = <&cpg 0xa5>, <&cpg 0xa6>; + }; + cpg: clock-controller@10420000 { compatible = "renesas,r9a09g047-cpg"; reg = <0 0x10420000 0 0x10000>;