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[isar-cip-core] ci: Require qemu-riscv64 sid target to succeed

Message ID 9521fcd9-6e54-4f68-bb3f-a7cd4e3f005e@siemens.com (mailing list archive)
State Accepted
Headers show
Series [isar-cip-core] ci: Require qemu-riscv64 sid target to succeed | expand

Commit Message

Jan Kiszka May 10, 2024, 2:55 p.m. UTC 
From: Jan Kiszka <jan.kiszka@siemens.com>

We are building against a snapshot that is generally working. Basically
all disturbances are now coming from our own code changes. To avoid
missing a riscv64 regression, require this job to succeed as well.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
 .gitlab-ci.yml | 1 -
 1 file changed, 1 deletion(-)
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Patch

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index aab55be5..72084f33 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -356,7 +356,6 @@  build:qemu-riscv64:
     use_rt: disable
     wic_targz: disable
     deploy: disable
-  allow_failure: true
 
 cve-checks:
   stage: cve-check