diff mbox series

[isar-cip-core,v2] u-boot: Update to 2024.01

Message ID fe9ba4d5-2475-4a1d-a641-47126d57b8fe@siemens.com (mailing list archive)
State Accepted
Headers show
Series [isar-cip-core,v2] u-boot: Update to 2024.01 | expand

Commit Message

Jan Kiszka Jan. 15, 2024, 2:10 p.m. UTC
From: Jan Kiszka <jan.kiszka@siemens.com>

Allows to drop the riscv patch.

This version switches us to the bootflow mechanism. The boot command is
simpler, but the secure config needs extra care to turn off all non-EFI
flows while keeping all switches that we need and that normally come via
too brought CONFIG_BOOTSTD_DEFAULTS.

u-boot-common is actually version-specific as it carries the sha.
Reflect that in the file name. Using ${PV} for its inclusion only works
directly, not via u-boot-qemu-common.inc, so do that from the respective
.bb files.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---

Changes in v2:
 - fix secure boot

 ...iscv-Fix-build-against-binutils-2.38.patch | 55 -------------------
 recipes-bsp/u-boot/files/secure-boot.cfg      | 17 ++++++
 recipes-bsp/u-boot/files/secure-boot.cfg.tmpl |  7 ---
 ...t-bbb_2022.07.bb => u-boot-bbb_2024.01.bb} |  6 +-
 ...t-common.inc => u-boot-common-2024.01.inc} |  9 +--
 ...022.07.bb => u-boot-qemu-arm64_2024.01.bb} |  3 +-
 ..._2022.07.bb => u-boot-qemu-arm_2024.01.bb} |  3 +-
 recipes-bsp/u-boot/u-boot-qemu-common.inc     |  3 +-
 ...2.07.bb => u-boot-qemu-riscv64_2024.01.bb} |  8 +--
 9 files changed, 27 insertions(+), 84 deletions(-)
 delete mode 100644 recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch
 create mode 100644 recipes-bsp/u-boot/files/secure-boot.cfg
 delete mode 100644 recipes-bsp/u-boot/files/secure-boot.cfg.tmpl
 rename recipes-bsp/u-boot/{u-boot-bbb_2022.07.bb => u-boot-bbb_2024.01.bb} (80%)
 rename recipes-bsp/u-boot/{u-boot-common.inc => u-boot-common-2024.01.inc} (74%)
 rename recipes-bsp/u-boot/{u-boot-qemu-arm64_2022.07.bb => u-boot-qemu-arm64_2024.01.bb} (87%)
 rename recipes-bsp/u-boot/{u-boot-qemu-arm_2022.07.bb => u-boot-qemu-arm_2024.01.bb} (87%)
 rename recipes-bsp/u-boot/{u-boot-qemu-riscv64_2022.07.bb => u-boot-qemu-riscv64_2024.01.bb} (65%)
diff mbox series

Patch

diff --git a/recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch b/recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch
deleted file mode 100644
index 6f8a2ae0..00000000
--- a/recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch
+++ /dev/null
@@ -1,55 +0,0 @@ 
-From 5df4b2299f86933fa79aa3bc6a3986fc7e55b7e0 Mon Sep 17 00:00:00 2001
-From: Alexandre Ghiti <alexandre.ghiti@canonical.com>
-Date: Mon, 3 Oct 2022 18:07:54 +0200
-Subject: [PATCH 1/2] riscv: Fix build against binutils 2.38
-
-The following description is copied from the equivalent patch for the
-Linux Kernel proposed by Aurelien Jarno:
-
->From version 2.38, binutils default to ISA spec version 20191213. This
-means that the csr read/write (csrr*/csrw*) instructions and fence.i
-instruction has separated from the `I` extension, become two standalone
-extensions: Zicsr and Zifencei. As the kernel uses those instruction,
-this causes the following build failure:
-
-arch/riscv/cpu/mtrap.S: Assembler messages:
-arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
-arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
-arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
-arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
-
-Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
-Tested-by: Heiko Stuebner <heiko@sntech.de>
-Tested-by: Christian Stewart <christian@paral.in>
-Reviewed-by: Rick Chen <rick@andestech.com>
----
- arch/riscv/Makefile | 11 ++++++++++-
- 1 file changed, 10 insertions(+), 1 deletion(-)
-
-diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
-index 0b80eb8d86..53d1194ffb 100644
---- a/arch/riscv/Makefile
-+++ b/arch/riscv/Makefile
-@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
- 	CMODEL = medany
- endif
- 
--ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
-+RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
-+
-+# Newer binutils versions default to ISA spec version 20191213 which moves some
-+# instructions from the I extension to the Zicsr and Zifencei extensions.
-+toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
-+ifeq ($(toolchain-need-zicsr-zifencei),y)
-+	RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
-+endif
-+
-+ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
- 	     -mcmodel=$(CMODEL)
- 
- PLATFORM_CPPFLAGS	+= $(ARCH_FLAGS)
--- 
-2.30.2
-
diff --git a/recipes-bsp/u-boot/files/secure-boot.cfg b/recipes-bsp/u-boot/files/secure-boot.cfg
new file mode 100644
index 00000000..95371626
--- /dev/null
+++ b/recipes-bsp/u-boot/files/secure-boot.cfg
@@ -0,0 +1,17 @@ 
+### Secure boot config
+# CONFIG_BOOTSTD_DEFAULTS is not set
+# CONFIG_BOOTMETH_CROS is not set
+# CONFIG_BOOTMETH_EXTLINUX is not set
+# CONFIG_BOOTMETH_EXTLINUX_PXE is not set
+# CONFIG_BOOTMETH_VBE is not set
+# CONFIG_BOOTMETH_SCRIPT is not set
+CONFIG_BOOTDELAY=-2
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="bootflow scan -lb; echo 'EFI Boot failed!'; sleep 1000; reset"
+CONFIG_USB_STORAGE=y
+CONFIG_EFI_PARTITION=y
+CONFIG_FS_FAT=y
+CONFIG_EFI_VARIABLES_PRESEED=y
+CONFIG_EFI_SECURE_BOOT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_EFI_SCROLL_ON_CLEAR_SCREEN=y
diff --git a/recipes-bsp/u-boot/files/secure-boot.cfg.tmpl b/recipes-bsp/u-boot/files/secure-boot.cfg.tmpl
deleted file mode 100644
index 6111007c..00000000
--- a/recipes-bsp/u-boot/files/secure-boot.cfg.tmpl
+++ /dev/null
@@ -1,7 +0,0 @@ 
-### Secure boot config
-CONFIG_BOOTDELAY=-2
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="setenv scan_dev_for_boot 'if test -e ${devtype} ${devnum}:${distro_bootpart} efi/boot/boot${EFI_ARCH}.efi; then load ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr_r} efi/boot/boot${EFI_ARCH}.efi; bootefi ${kernel_addr_r} ${fdtcontroladdr}; fi'; run distro_bootcmd; echo 'EFI Boot failed!'; sleep 1000; reset"
-CONFIG_EFI_VARIABLES_PRESEED=y
-CONFIG_EFI_SECURE_BOOT=y
-CONFIG_FIT_SIGNATURE=y
diff --git a/recipes-bsp/u-boot/u-boot-bbb_2022.07.bb b/recipes-bsp/u-boot/u-boot-bbb_2024.01.bb
similarity index 80%
rename from recipes-bsp/u-boot/u-boot-bbb_2022.07.bb
rename to recipes-bsp/u-boot/u-boot-bbb_2024.01.bb
index 6632bb6c..e727c5af 100644
--- a/recipes-bsp/u-boot/u-boot-bbb_2022.07.bb
+++ b/recipes-bsp/u-boot/u-boot-bbb_2024.01.bb
@@ -1,7 +1,7 @@ 
 #
 # CIP Core, generic profile
 #
-# Copyright (c) Siemens AG, 2022
+# Copyright (c) Siemens AG, 2022-2024
 #
 # Authors:
 #  Jan Kiszka <jan.kiszka@siemens.com>
@@ -9,13 +9,11 @@ 
 # SPDX-License-Identifier: MIT
 #
 
-require u-boot-common.inc
+require u-boot-common-${PV}.inc
 
 U_BOOT_CONFIG = "am335x_evm_defconfig"
 U_BOOT_BIN = "all"
 
-EFI_ARCH = "arm"
-
 do_prepare_build:append() {
     echo "MLO u-boot.img /usr/lib/u-boot/${MACHINE}" > \
         ${S}/debian/u-boot-${MACHINE}.install
diff --git a/recipes-bsp/u-boot/u-boot-common.inc b/recipes-bsp/u-boot/u-boot-common-2024.01.inc
similarity index 74%
rename from recipes-bsp/u-boot/u-boot-common.inc
rename to recipes-bsp/u-boot/u-boot-common-2024.01.inc
index 0486cdaf..69427322 100644
--- a/recipes-bsp/u-boot/u-boot-common.inc
+++ b/recipes-bsp/u-boot/u-boot-common-2024.01.inc
@@ -1,7 +1,7 @@ 
 #
 # CIP Core, generic profile
 #
-# Copyright (c) Siemens AG, 2022
+# Copyright (c) Siemens AG, 2022-2024
 #
 # Authors:
 #  Jan Kiszka <jan.kiszka@siemens.com>
@@ -14,10 +14,10 @@  require recipes-bsp/u-boot/u-boot-custom.inc
 SRC_URI += " \
     https://ftp.denx.de/pub/u-boot/u-boot-${PV}.tar.bz2 \
     file://rules.tmpl;subdir=debian"
-SRC_URI[sha256sum] = "92b08eb49c24da14c1adbf70a71ae8f37cc53eeb4230e859ad8b6733d13dcf5e"
+SRC_URI[sha256sum] = "b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3"
 
 SRC_URI:append:secureboot = " \
-    file://secure-boot.cfg.tmpl"
+    file://secure-boot.cfg"
 
 S = "${WORKDIR}/u-boot-${PV}"
 
@@ -27,9 +27,6 @@  DEBIAN_BUILD_DEPENDS:append:secureboot = ", \
     openssl, pesign, secure-boot-secrets, python3-openssl:native"
 DEPENDS:append:secureboot = " secure-boot-secrets"
 
-TEMPLATE_FILES:append:secureboot = " secure-boot.cfg.tmpl"
-TEMPLATE_VARS:append:secureboot = " EFI_ARCH"
-
 do_prepare_build:append:secureboot() {
     sed -ni '/### Secure boot config/q;p' ${S}/configs/${U_BOOT_CONFIG}
     cat ${WORKDIR}/secure-boot.cfg >> ${S}/configs/${U_BOOT_CONFIG}
diff --git a/recipes-bsp/u-boot/u-boot-qemu-arm64_2022.07.bb b/recipes-bsp/u-boot/u-boot-qemu-arm64_2024.01.bb
similarity index 87%
rename from recipes-bsp/u-boot/u-boot-qemu-arm64_2022.07.bb
rename to recipes-bsp/u-boot/u-boot-qemu-arm64_2024.01.bb
index 29ca0a55..9ce62937 100644
--- a/recipes-bsp/u-boot/u-boot-qemu-arm64_2022.07.bb
+++ b/recipes-bsp/u-boot/u-boot-qemu-arm64_2024.01.bb
@@ -9,8 +9,7 @@ 
 # SPDX-License-Identifier: MIT
 #
 
+require u-boot-common-${PV}.inc
 require u-boot-qemu-common.inc
 
 U_BOOT_CONFIG = "qemu_arm64_defconfig"
-
-EFI_ARCH = "aa64"
diff --git a/recipes-bsp/u-boot/u-boot-qemu-arm_2022.07.bb b/recipes-bsp/u-boot/u-boot-qemu-arm_2024.01.bb
similarity index 87%
rename from recipes-bsp/u-boot/u-boot-qemu-arm_2022.07.bb
rename to recipes-bsp/u-boot/u-boot-qemu-arm_2024.01.bb
index cdad19a3..8540bfc5 100644
--- a/recipes-bsp/u-boot/u-boot-qemu-arm_2022.07.bb
+++ b/recipes-bsp/u-boot/u-boot-qemu-arm_2024.01.bb
@@ -9,8 +9,7 @@ 
 # SPDX-License-Identifier: MIT
 #
 
+require u-boot-common-${PV}.inc
 require u-boot-qemu-common.inc
 
 U_BOOT_CONFIG = "qemu_arm_defconfig"
-
-EFI_ARCH = "arm"
diff --git a/recipes-bsp/u-boot/u-boot-qemu-common.inc b/recipes-bsp/u-boot/u-boot-qemu-common.inc
index b222155c..0bf7b621 100644
--- a/recipes-bsp/u-boot/u-boot-qemu-common.inc
+++ b/recipes-bsp/u-boot/u-boot-qemu-common.inc
@@ -1,7 +1,7 @@ 
 #
 # CIP Core, generic profile
 #
-# Copyright (c) Siemens AG, 2022
+# Copyright (c) Siemens AG, 2022-2024
 #
 # Authors:
 #  Jan Kiszka <jan.kiszka@siemens.com>
@@ -10,7 +10,6 @@ 
 #
 
 inherit deploy-firmware
-require recipes-bsp/u-boot/u-boot-common.inc
 
 U_BOOT_BIN = "u-boot.bin"
 
diff --git a/recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb b/recipes-bsp/u-boot/u-boot-qemu-riscv64_2024.01.bb
similarity index 65%
rename from recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb
rename to recipes-bsp/u-boot/u-boot-qemu-riscv64_2024.01.bb
index 8dfac457..43b9e28d 100644
--- a/recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb
+++ b/recipes-bsp/u-boot/u-boot-qemu-riscv64_2024.01.bb
@@ -1,7 +1,7 @@ 
 #
 # CIP Core, generic profile
 #
-# Copyright (c) Siemens AG, 2022
+# Copyright (c) Siemens AG, 2022-2024
 #
 # Authors:
 #  Jan Kiszka <jan.kiszka@siemens.com>
@@ -9,14 +9,10 @@ 
 # SPDX-License-Identifier: MIT
 #
 
+require u-boot-common-${PV}.inc
 require u-boot-qemu-common.inc
 
 # we run as OpenSBI payload, hence use smode
 U_BOOT_CONFIG = "${MACHINE}_smode_defconfig"
 
-EFI_ARCH = "riscv64"
-
-SRC_URI += " \
-    file://riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch"
-
 U_BOOT_BIN = "u-boot.bin"