mbox series

[0/3] Add sanity check for interleave setup

Message ID 165999244272.493131.1975513183227389633.stgit@djiang5-desk4.jf.intel.com
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Series Add sanity check for interleave setup | expand

Message

Dave Jiang Aug. 8, 2022, 9:06 p.m. UTC 
The small series adds sanity check for the combination of interleave ways
and interleave granularity during region and port configuration. The
calculation references CXL spec 3.0 8.2.4.19.13 implementation note #3. The
checks also added HDM CAP retrieval for the support of new interleave ways
where 3, 6, and 12 ways support as well as 16 ways support.

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Dave Jiang (3):
      cxl: Add check for result of interleave ways plus granularity combo
      cxl: Add CXL spec v3.0 interleave support
      tools/testing/cxl: Add interleave check support to mock cxl port device


 drivers/cxl/core/hdm.c       |  4 +++
 drivers/cxl/core/region.c    | 17 +++++++++-
 drivers/cxl/cxl.h            | 13 ++++++++
 drivers/cxl/cxlmem.h         | 60 ++++++++++++++++++++++++++++++++++++
 tools/testing/cxl/test/cxl.c |  2 ++
 5 files changed, 95 insertions(+), 1 deletion(-)

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