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[0/7] CXL region creation fixes for 6.1

Message ID 166752181697.947915.744835334283138352.stgit@dwillia2-xfh.jf.intel.com
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Series CXL region creation fixes for 6.1 | expand

Message

Dan Williams Nov. 4, 2022, 12:30 a.m. UTC
On the way to fixing and regression testing Jonathan's report of CXL
region creation failure on a single-port host bridge configuration [1],
several other fixes fell out. Details in the individual commits, but the
fixes mostly revolve around leaked references and other bugs in the
region creation failure case. All but the last fix are tagged for
-stable. The final fix is cosmetic, but leaving it unfixed gives the
appearance of another memory leak condition.

Lastly, the problematic configuration is added to cxl_test to allow for
regression testing it going forward.

[1]: http://lore.kernel.org/r/20221010172057.00001559@huawei.com

---

Dan Williams (7):
      cxl/region: Fix region HPA ordering validation
      cxl/region: Fix cxl_region leak, cleanup targets at region delete
      cxl/pmem: Fix cxl_pmem_region and cxl_memdev leak
      tools/testing/cxl: Fix some error exits
      tools/testing/cxl: Add a single-port host-bridge regression config
      cxl/region: Fix 'distance' calculation with passthrough ports
      cxl/region: Recycle region ids


 drivers/cxl/core/pmem.c      |    2 
 drivers/cxl/core/port.c      |   11 +-
 drivers/cxl/core/region.c    |   43 ++++++
 drivers/cxl/cxl.h            |    4 -
 drivers/cxl/pmem.c           |  100 +++++++++-----
 tools/testing/cxl/test/cxl.c |  301 +++++++++++++++++++++++++++++++++++++++---
 6 files changed, 400 insertions(+), 61 deletions(-)

base-commit: 4f1aa35f1fb7d51b125487c835982af792697ecb